公开(公告)号：US20140210044A1

公开(公告)日：2014-07-31

申请号：US14076419

申请日：2013-11-11

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan LEE

IPC: H01L27/02 ,  H01L27/07

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract translation: 公开了一种包括顺序地设置在基板上的第一绝缘层和第二绝缘层的半导体器件。 第一导电线和第二导线设置在第一绝缘层中，并且第一和第二导线中的每一个具有第一端和第二端，其中第一和第二导线的第二端耦合到每个 其他。 第一绕组部分和第二绕组部分设置在第二绝缘层中，并且第一和第二绕组部分中的每一个包括从内向外布置的第三导线和第四导线。 第三和第四导线中的每一个具有第一端和第二端，其中第一和第二导线与第三导线的至少一部分重叠。

公开(公告)号：USD706263S1

公开(公告)日：2014-06-03

申请号：US29444766

申请日：2013-02-04

Applicant: Via Technologies, Inc.

Designer： Chia-Yi Lin ,  Neng-An Kuo

公开(公告)号：US20140129818A1

公开(公告)日：2014-05-08

申请号：US14017378

申请日：2013-09-04

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Kai LI ,  Jiangbo WANG ,  Wei YIN

IPC: G06F9/44

CPC classification number: G06F9/4403 ,  G06F1/24 ,  G06F21/572 ,  G06F21/575 ,  G06F21/79

Abstract: The present invention provides an electronic device including a write-once-then-read-only register, a chipset, a read-only memory, a flash memory and a central processor. The write-once-then-read-only register is arranged to store a determination value. The chipset is arranged to produce a CPU reset signal. The read-only memory is implemented in the chipset, and has a first memory block which corresponds to a predetermined address and is used to store a first instruction. The flash memory is coupled to the chipset, and has a second memory block which corresponds to the predetermined address and is used to store a second instruction. The central processor is arranged to determine the location of the predetermined address according to the CPU reset signal and the determination value.

Abstract translation: 本发明提供一种电子设备，其包括一次写入只读寄存器，芯片组，只读存储器，闪存和中央处理器。 一次写入只读寄存器被布置成存储确定值。 芯片组被布置成产生CPU复位信号。 只读存储器在芯片组中实现，并且具有对应于预定地址并用于存储第一指令的第一存储器块。 闪存耦合到芯片组，并且具有对应于预定地址的第二存储器块，并用于存储第二指令。 中央处理器被配置为根据CPU复位信号和确定值确定预定地址的位置。

公开(公告)号：US20140115284A1

公开(公告)日：2014-04-24

申请号：US13736092

申请日：2013-01-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Shou-Di Lee ,  Guang-Hui Wu ,  Hai-Bin Shen

IPC: G06F12/16

CPC classification number: G06F11/1438 ,  G06F11/1402 ,  G06F11/1441 ,  G06F12/16 ,  G06F2201/805 ,  G06F2201/85

Abstract: A progress recording method and a corresponding recovering method adapted to an encoding operation performed on a storage area of a storage device are provided. The progress recording method includes the following steps. A variable set is initialized and stored. The encoding operation includes a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set. The flag variables are used for recording execution progresses of the sub-operations. When each of the sub-operations is executed, the corresponding flag variable in the variable set is updated according to the execution progress of the sub-operation.

Abstract translation: 提供了一种适用于对存储装置的存储区域执行的编码操作的进度记录方法和相应的恢复方法。 进度记录方法包括以下步骤。 初始化并存储变量集。 编码操作包括多个子操作，并且每个子操作对应于变量集合中的至少一个标志变量。 标志变量用于记录子操作的执行进度。 当执行每个子操作时，根据子操作的执行进度来更新变量集中的相应标志变量。

公开(公告)号：US08687681B2

公开(公告)日：2014-04-01

申请号：US13861216

申请日：2013-04-11

Applicant: VIA Technologies, Inc.

Inventor： Chin-Fa Hsiao ,  Shih-Min Lin

IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC classification number: H04L7/0079 ,  H04B17/0085

Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.

Abstract translation: 接收机包括CDR电路，串并转换器和测试模块。 CDR电路用于接收串联输入的测试信号组，并接收测试信号组的发送频率以获得时钟信号，其中时钟信号用于提供接收机的工作频率。 串并转换器用于接收由CDR电路输出的测试信号组，并将串行输入的测试信号组转换为并行输出的多个测试字节，其中每个测试字节具有多位数据 。 测试模块用于接收测试字节和时钟信号，并比较测试字节的两个相邻字节，以确定两个相邻测试字节是否完全相同。

公开(公告)号：US20140059358A1

公开(公告)日：2014-02-27

申请号：US14053953

申请日：2013-10-15

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F9/30076 ,  G06F9/30101 ,  G06F21/31 ,  G06F21/71 ,  G06F21/78 ,  G06F21/79

Abstract: A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key.

Abstract translation: 微处理器包括具有地址的型号特定寄存器（MSR），具有第一预定值制造的保险丝和控制寄存器。 微处理器首先将第一预定值从保险丝加载到控制寄存器中。 在最初将第一预定值加载到控制寄存器之后，微处理器还从包括微处理器的计算机系统的系统软件接收第二预定值。 微处理器通过提供通过利用在微处理器的第一实例中制造的秘密密钥加密第一预定值和MSR地址的功能产生的第一密码的指令来禁止对MSR的访问，并使得能够通过指令访问MSR 其提供通过用秘密密钥加密第二预定值的功能和MSR地址产生的第二密码。

公开(公告)号：US20140047142A1

公开(公告)日：2014-02-13

申请号：US14048388

申请日：2013-10-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Jiin LAI ,  Buheng XU ,  Jinkuan TANG

IPC: G06F13/38

CPC classification number: G06F13/385 ,  G06F11/08 ,  G06F13/00 ,  G06F13/12

Abstract: A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device.

Abstract translation: 提供了一种数据传输系统和方法。 数据传输方法接收主机发送的第二格式数据包; 解码由主机发送的第二格式数据分组，并将解码的第二格式数据分组转换为第一格式数据分组; 将第一格式数据分组发送到第一设备; 响应于第一格式数据分组接收由第一设备发送的传输响应，确定是否向主机发送传输响应，并且当传输响应不需要发送到主机时执行重试流程。 优选地，第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备，并且第二格式数据分组与第二设备一致。

公开(公告)号：US20140025864A1

公开(公告)日：2014-01-23

申请号：US13908736

申请日：2013-06-03

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Bo ZHANG ,  Chen XIU

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0802 ,  G06F2212/7202 ,  G06F2212/7203

Abstract: A data storage device with a FLASH memory and an operating method for the data storage device are disclosed. According to the disclosure, the space of the FLASH memory is allocated to include groups of data blocks, a plurality of shared cache blocks (SCBs) and a plurality of dedicated cache blocks (DCBs). Each SCB is shared by one group of data blocks, for the write data storage when any data block of the group of data blocks is exhausted. The DCBs are allocated for the hot data storage. Each DCB corresponds to one hot logical block.

Abstract translation: 公开了具有FLASH存储器和数据存储装置的操作方法的数据存储装置。 根据本公开，FLASH存储器的空间被分配为包括数据块组，多个共享高速缓存块（SCB）和多个专用高速缓存块（DCB））。 当数据块组中的任何数据块用完时，每个SCB由一组数据块共享，用于写数据存储。 DCB分配给热数据存储。 每个DCB对应于一个热逻辑块。

公开(公告)号：US20140013058A1

公开(公告)日：2014-01-09

申请号：US13872527

申请日：2013-04-29

Applicant: VIA Technologies, Inc.

Inventor： Rodney E. Hooker ,  Colin Eddy

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F2212/6028

Abstract: A microprocessor includes a translation lookaside buffer, a request to load a page table entry into the microprocessor generated in response to a miss of a virtual address in the translation lookaside buffer, and a prefetch unit. The prefetch unit receives a physical address of a first cache line that includes the requested page table entry and responsively generates a request to prefetch into the microprocessor a second cache line that is the next physically sequential cache line to the first cache line.

Abstract translation: 微处理器包括翻译后备缓冲器，将页表条目加载到微处理器中的请求，该请求响应于翻译后备缓冲器中的虚拟地址的错过而产生，以及预取单元。 预取单元接收包括所请求的页表条目的第一高速缓存行的物理地址，并且响应地生成将第二高速缓存行预取到微处理器的请求，该第二高速缓存行是到第一高速缓存行的下一物理连续高速缓存行。

公开(公告)号：US20140000953A1

公开(公告)日：2014-01-02

申请号：US14020104

申请日：2013-09-06

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/465 ,  H05K1/0298 ,  H05K3/045 ,  H05K3/108 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0554 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.

Abstract translation: 电路基板包括基底层，第一图案化导电层，电介质层，导电块和第二图案化导电层。 第一图案化导电层设置在基底层上并具有第一焊盘。 电介质层设置在基底层上并覆盖第一图案化导电层，其中电介质层具有开口，第一焊盘由开口露出。 导电块设置在开口中并覆盖第一垫。 第二图案化导电层设置在电介质层的表面上并具有第二焊盘，其中第二焊盘和导电块一体形成。