公开(公告)号：US10119995B2

公开(公告)日：2018-11-06

申请号：US14149822

申请日：2014-01-08

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang ,  Wei-Cheng Chen

IPC: G01R1/073 ,  G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L21/84 ,  H01R12/06

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

公开(公告)号：US20170025343A1

公开(公告)日：2017-01-26

申请号：US15284514

申请日：2016-10-03

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US09497864B2

公开(公告)日：2016-11-15

申请号：US13898486

申请日：2013-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H05K3/28

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。

公开(公告)号：US20140000953A1

公开(公告)日：2014-01-02

申请号：US14020104

申请日：2013-09-06

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/465 ,  H05K1/0298 ,  H05K3/045 ,  H05K3/108 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0554 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.

Abstract translation: 电路基板包括基底层，第一图案化导电层，电介质层，导电块和第二图案化导电层。 第一图案化导电层设置在基底层上并具有第一焊盘。 电介质层设置在基底层上并覆盖第一图案化导电层，其中电介质层具有开口，第一焊盘由开口露出。 导电块设置在开口中并覆盖第一垫。 第二图案化导电层设置在电介质层的表面上并具有第二焊盘，其中第二焊盘和导电块一体形成。

公开(公告)号：US09324580B2

公开(公告)日：2016-04-26

申请号：US14789998

申请日：2015-07-02

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/48 ,  H01L21/32 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L21/32 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81449 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/8148 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/113 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 该过程包括以下步骤。 提供载体。 导电层和电介质层被放置在载体上，并且导电层位于载体和电介质层之间。 图案化电介质层以形成具有部分暴露导电层的第一开口的图案化电介质层。 在导电层的暴露部分上形成弧形槽。 形成具有分别连接第一开口的第二开口的第一图案化光致抗蚀剂层。 形成导电结构，其中每个导电结构一体地形成，并且包括衬垫部分，连接部分和突出部分; 第二开口，第一开口和弧形槽分别填充有垫部分，连接部分和突出部分。 去除第一图案化光致抗蚀剂层，载体和导电层。

公开(公告)号：US20240421096A1

公开(公告)日：2024-12-19

申请号：US18476281

申请日：2023-09-27

Applicant: VIA Technologies, Inc.

Inventor： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Chen-Yueh Kung

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A manufacturing method of an electronic package includes the following steps. Multiple chips are temporarily fixed to a temporary carrier. At least one bridge element is installed on the adjacent chips. A base dielectric layer covering a temporary bonding layer, the chips, and the bridge element is formed. A material of the base dielectric layer includes a silicate composite material. Multiple base conductive vias and a redistribution structure are respectively formed on the chips and the base dielectric layer. Multiple conductive bumps are formed on the redistribution structure. In addition, an electronic package is also provided, which may be produced by the manufacturing method.

公开(公告)号：US20180267084A1

公开(公告)日：2018-09-20

申请号：US15984420

申请日：2018-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang ,  Wei-Cheng Chen

IPC: G01R1/073

CPC classification number: G01R1/07314 ,  G01R1/07378

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

公开(公告)号：US09532467B2

公开(公告)日：2016-12-27

申请号：US14020104

申请日：2013-09-06

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/04 ,  H05K3/10

CPC classification number: H05K3/465 ,  H05K1/0298 ,  H05K3/045 ,  H05K3/108 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0554 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.

Abstract translation: 电路基板包括基底层，第一图案化导电层，电介质层，导电块和第二图案化导电层。 第一图案化导电层设置在基底层上并具有第一焊盘。 电介质层设置在基底层上并覆盖第一图案化导电层，其中电介质层具有开口，第一焊盘由开口露出。 导电块设置在开口中并覆盖第一焊盘。 第二图案化导电层设置在电介质层的表面上并具有第二焊盘，其中第二焊盘和导电块一体形成。

公开(公告)号：US20150061119A1

公开(公告)日：2015-03-05

申请号：US14054850

申请日：2013-10-16

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H01L23/12 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

Abstract: A circuit substrate includes a circuit stack, a patterned conductive layer, a dielectric layer, and a plurality of thickening conductive layers. The circuit stack has a surface. The patterned conductive layer is located on the surface of the circuit stack and has a plurality of traces. Each of the traces has a bonding segment. The dielectric layer is located on the surface of the circuit stack and covers the patterned conductive layer. Besides, the dielectric layer has a plurality of bonding openings Each of the bonding openings exposes the corresponding bonding segment. Each of the thickening conductive layers is located on the corresponding bonding segment. A semiconductor package structure having the above circuit substrate and a process for fabricating a circuit substrate are also provided.

Abstract translation: 电路基板包括电路堆叠，图案化导电层，电介质层和多个增厚导电层。 电路堆叠有一个表面。 图案化的导电层位于电路堆叠的表面上并且具有多个迹线。 每条迹线都有一个粘结段。 电介质层位于电路堆叠的表面上并覆盖图案化的导电层。 此外，电介质层具有多个接合开口。每个接合开口暴露相应的接合段。 每个增稠导电层位于相应的粘结段上。 还提供了具有上述电路基板和制造电路基板的工艺的半导体封装结构。

公开(公告)号：US20140293547A1

公开(公告)日：2014-10-02

申请号：US13898486

申请日：2013-05-21

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung

IPC: H05K1/18 ,  H05K3/40

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/10 ,  H01L2224/16157 ,  H01L2224/73204 ,  H05K1/112 ,  H05K1/119 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0723 ,  H05K2203/107 ,  H05K2203/1476 ,  Y10T29/49156

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract translation: 电路基板具有以下元件。 层叠电路结构具有与其相对的第一表面和第二表面。 第一图案化内导电层设置在第一表面上并具有多个焊盘。 第一图案化外导电层设置在图案化的内导电层上并且具有多个导电柱，其中第一导电柱中的每一个位于相应的第一焊盘上。 第一介电层覆盖第一表面，第一图案化内导电层和第一图案化外导电层，并且具有多个第一凹部，其中第一凹部暴露对应的第一导电柱的顶部和侧面。 应用上述电路基板的半导体封装结构及其制造方法也在这里提供。