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    DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE
    101.
    发明申请
    DUAL-DEPTH SELF-ALIGNED ISOLATION STRUCTURE FOR A BACK GATE ELECTRODE 失效
    用于背盖电极的双深度自对准隔离结构

    公开(公告)号：US20120256260A1

    公开(公告)日：2012-10-11

    申请号：US13082491

    申请日：2011-04-08

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66742 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648

    摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

    摘要翻译： 通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。 将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。 氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。 将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。 在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

    Integrated circuit with on chip planar diode and CMOS devices
    104.
    发明授权
    Integrated circuit with on chip planar diode and CMOS devices 有权
    集成电路与片上平面二极管和CMOS器件

    公开(公告)号：US09048108B2

    公开(公告)日：2015-06-02

    申请号：US13478080

    申请日：2012-05-22

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/8238 ,  H01L27/06

    CPC分类号： H01L27/0629 ,  H01L29/0847 ,  H01L29/8611 ,  H01L29/868

    摘要： An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.

    摘要翻译： 在同一芯片上形成二极管和一个或多个CMOS器件的电路，平面二极管和方法。 该方法包括将二极管区域中的衬底的一部分与其它衬底区域电隔离。 该方法还包括使二极管区域中的衬底凹陷。 该方法还包括在二极管区域中外延形成在衬底上方的第一掺杂层，并在二极管区域中外延地形成第一掺杂层上方的第二掺杂层。

    MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation
    107.
    发明授权
    MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation 有权
    具有薄半导体通道的MOSFET和具有增强的结隔离的嵌入式应力源

    公开(公告)号：US08575698B2

    公开(公告)日：2013-11-05

    申请号：US13283308

    申请日：2011-10-27

    申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

    摘要： A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.

    摘要翻译： 场效应晶体管结构，其使用薄绝缘体上半导体通道来控制器件的静电完整性。 嵌入的应力源在源极/漏极区域中从硅衬底中的模板通过在源极/漏极区域中的掩埋氧化物中形成的开口外延生长。 此外，在嵌入式应力器和位于沟道正下方的掩埋氧化物层下面的半导体区域之间形成介电层，以抑制结电容和漏电。

    ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS
    108.
    发明申请
    ENHANCEMENT OF CHARGE CARRIER MOBILITY IN TRANSISTORS 失效
    晶体管中载流子迁移的增强

    公开(公告)号：US20130082328A1

    公开(公告)日：2013-04-04

    申请号：US13251783

    申请日：2011-10-03

    申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78654

    摘要： Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

    摘要翻译： 公开了包括应激源的晶体管器件。 一个这样的晶体管器件包括沟道区，电介质层和半导体衬底。 沟道区域被配置为在源极区域和漏极区域之间提供导电沟道。 此外，电介质层在沟道区下方，并被配置为使沟道区电绝缘。 此外，半导体衬底在沟道区域下方和介电层下方包括在半导体衬底的顶表面处的位错缺陷，其中位错缺陷共同定向以在沟道区域施加压缩应变，使得载流子 渠道区域的移动性得到增强。

    Raised source/drain structure for enhanced strain coupling from stress liner
    109.
    发明授权
    Raised source/drain structure for enhanced strain coupling from stress liner 有权
    用于增强应力衬垫的应变耦合的源/漏结构

    公开(公告)号：US08338260B2

    公开(公告)日：2012-12-25

    申请号：US12760250

    申请日：2010-04-14

    申请人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

    发明人： Kangguo Cheng ,  Bruce Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam Shahidi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78654 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78618

    摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.

    摘要翻译： 提供一种晶体管，其包括衬底上方的掩埋氧化物层。 硅层在掩埋氧化物层之上。 栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。 氮化物衬垫与栅堆叠相邻。 氧化物衬垫与氮化物衬垫相邻。 一组具有包括硅层的一部分的部分的凸起的源/漏区。 所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

    Integrated Circuit Diode
    110.
    发明申请
    Integrated Circuit Diode 有权
    集成电路二极管

    公开(公告)号：US20120286364A1

    公开(公告)日：2012-11-15

    申请号：US13104542

    申请日：2011-05-10

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/8238

    CPC分类号： H01L27/0727 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203

    摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

    摘要翻译： 一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层 在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层 使用第二外延生长工艺在第一二极管层上。