公开(公告)号：US07967062B2

公开(公告)日：2011-06-28

申请号：US11424642

申请日：2006-06-16

申请人： Levi A. Campbell ,  Richard C. Chu ,  Michael J. Ellsworth, Jr. ,  Keith E. Fogel ,  Madhusudan K. Iyengar ,  Roger R. Schmidt ,  Robert E. Simons

发明人： Levi A. Campbell ,  Richard C. Chu ,  Michael J. Ellsworth, Jr. ,  Keith E. Fogel ,  Madhusudan K. Iyengar ,  Roger R. Schmidt ,  Robert E. Simons

IPC分类号： F28F7/00 ,  H05K7/20

CPC分类号： H01L23/3677 ,  H01L2224/78301 ,  Y10T29/49128 ,  Y10T29/4935 ,  H01L2924/00014

摘要： A composite interface and methods of fabrication are provided for coupling a cooling assembly to an electronic device. The interface includes a plurality of thermally conductive wires formed of a first material having a first thermal conductivity, and a thermal interface material at least partially surrounding the wires. The interface material, which thermally interfaces the cooling assembly to a surface to be cooled of the electronic device, is a second material having a second thermal conductivity, wherein the first thermal conductivity is greater than the second thermal conductivity. At least some wires reside partially over a first region of higher heat flux and extend partially over a second region of lower heat flux, wherein the first and second regions are different regions of the surface to be cooled. These wires function as thermal spreaders facilitating heat transfer from the surface to be cooled to the cooling assembly.

摘要翻译： 提供了复合界面和制造方法，用于将冷却组件连接到电子设备。 界面包括由具有第一导热性的第一材料形成的多个导热丝，以及至少部分地围绕线的热界面材料。 将冷却组件与待冷却的电子设备的表面热接合的界面材料是具有第二导热性的第二材料，其中第一热导率大于第二导热系数。 至少一些线部分地位于较高热通量的第一区域上，并部分地延伸在较低热通量的第二区域上，其中第一和第二区域是待冷却表面的不同区域。 这些电线作为热扩散器起促进从待冷却表面到冷却组件的热传递。

公开(公告)号：US20110048516A1

公开(公告)日：2011-03-03

申请号：US12713581

申请日：2010-02-26

申请人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi

IPC分类号： H01L31/10 ,  H01L31/0216

CPC分类号： H01L31/068 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/547 ,  Y02E10/548

摘要： A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.

摘要翻译： 制造多结光伏（PV）电池的方法包括在衬底上提供包括多个结的叠层，所述多个结中的每一个具有相应的带隙，其中所述多个结从具有最小带隙的结点排序 位于具有最大带隙位于堆叠顶部的基底上的基底上; 在具有最大带隙的结的顶部上形成顶部金属层，顶部金属层具有拉伸应力; 将顶部柔性基底粘附到金属层上; 并且在基板的断裂处从基板剥离半导体层，其中响应于顶部金属层中的拉伸应力形成断裂。

公开(公告)号：US20100307591A1

公开(公告)日：2010-12-09

申请号：US12713572

申请日：2010-02-26

申请人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

发明人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Keith E. Fogel ,  Devendra Sadana ,  Davood Shahrjerdi ,  Brent A. Wacaser

IPC分类号： H01L31/0304 ,  H01L31/18

CPC分类号： H01L31/0304 ,  H01L31/0725 ,  H01L31/074 ,  H01L31/075 ,  H01L31/076 ,  H01L31/184 ,  H01L31/1892 ,  Y02E10/548

摘要： A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer.

摘要翻译： 一种形成单结光伏电池的方法包括在半导体衬底的表面上形成掺杂剂层; 将掺杂剂层扩散到半导体衬底中以形成半导体衬底的掺杂层; 在所述掺杂层上形成金属层，其中所述金属层中的拉伸应力构造成在所述半导体衬底中引起断裂; 在断裂时从半导体衬底去除半导体层; 以及使用半导体层形成单结光伏电池。 单结光伏电池包括掺杂剂，该掺杂层包含扩散到半导体衬底中的掺杂剂; 形成在掺杂层上的图案化导电层; 半导体层，其包括位于掺杂层的与图案化导电层相对的表面上的掺杂层上的半导体衬底; 以及形成在半导体层上的欧姆接触层。

公开(公告)号：US07842940B2

公开(公告)日：2010-11-30

申请号：US12062164

申请日：2008-04-03

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US20100123205A1

公开(公告)日：2010-05-20

申请号：US12272129

申请日：2008-11-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US07704852B2

公开(公告)日：2010-04-27

申请号：US11871694

申请日：2007-10-12

申请人： Keith E. Fogel ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Haizhou Yin

发明人： Keith E. Fogel ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Haizhou Yin

IPC分类号： H01L21/76

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.

摘要翻译： 本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。 用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。 第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。 本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。 特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

公开(公告)号：US07691733B2

公开(公告)日：2010-04-06

申请号：US12062749

申请日：2008-04-04

申请人： Keith E. Fogel ,  Kam-Leung Lee ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Haizhou Yin

发明人： Keith E. Fogel ,  Kam-Leung Lee ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Haizhou Yin

IPC分类号： H01L21/20

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

摘要翻译： 本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。 用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。 第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。 特别地，本发明提供熔融重结晶ATR方法，其单独使用或与非熔融再结晶ATR方法组合使用，其中通过介电填充沟槽界定的选定的Si区域被诱导通过以下步骤进行取向改变： 熔融前体变形，激光熔化和无角点缺陷的模板重结晶。

公开(公告)号：US20100006985A1

公开(公告)日：2010-01-14

申请号：US12170459

申请日：2008-07-10

申请人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

发明人： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/76245

摘要： A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.

摘要翻译： 提供了一种制造绝缘体上硅衬底的方法。 这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。 随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。 上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。 然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层 从底层半导体区域。 可以在非高p型掺杂外延层同时退火的同时执行这种处理。

公开(公告)号：US20090134460A1

公开(公告)日：2009-05-28

申请号：US12363239

申请日：2009-01-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L27/00 ,  H01L21/71

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US07485539B2

公开(公告)日：2009-02-03

申请号：US11332564

申请日：2006-01-13

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/76

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。