公开(公告)号：US06291137B1

公开(公告)日：2001-09-18

申请号：US09234380

申请日：1999-01-20

申请人： Christopher F. Lyons ,  Michael K. Templeton ,  Kathleen R. Early

发明人： Christopher F. Lyons ,  Michael K. Templeton ,  Kathleen R. Early

IPC分类号： G03C500

CPC分类号： H01L21/76885 ,  H01L21/28132 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.

摘要翻译： 在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化侧壁模板，其中所述导电膜的第二部分被暴露，所述侧壁模板在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述侧壁模板上沉积侧壁膜，所述侧壁膜具有邻近所述侧壁模板的侧壁的垂直部分和在不邻近所述侧壁模板的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的侧壁模板; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。

公开(公告)号：US06245493B1

公开(公告)日：2001-06-12

申请号：US09205738

申请日：1998-12-04

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur ,  Michael K. Templeton ,  Christopher F. Lyons

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Sanjay K. Yedur ,  Michael K. Templeton ,  Christopher F. Lyons

IPC分类号： G03F700

CPC分类号： H01L21/0276 ,  G03F7/091 ,  G03F7/16 ,  H01L21/3105

摘要： A method for creating a roughened surface on a material exposed to light during a photolithographic process is provided. The roughened surface is created on a surface of the material via a plasma etch process. The roughened surface diffuses light incident to the material such that the diffused light causes insubstantial damage to a photoresist subsequently formed on the material.

摘要翻译： 提供了一种在光刻过程中在暴露于光的材料上产生粗糙表面的方法。 通过等离子体蚀刻工艺在材料的表面上形成粗糙表面。 粗糙表面扩散入射到材料的光，使得漫射的光对随后在材料上形成的光致抗蚀剂造成非实质的损坏。

公开(公告)号：US06239031B1

公开(公告)日：2001-05-29

申请号：US09487493

申请日：2000-01-19

申请人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyah ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Basab Bandyopadhyah ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21302

CPC分类号： G03F9/7076 ,  G03F9/70 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

摘要翻译： 使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本透明的层。 实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。 分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。 由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。

公开(公告)号：US06210050B1

公开(公告)日：2001-04-03

申请号：US09203297

申请日：1998-12-01

申请人： Marina V. Plat ,  Christopher F. Lyons

发明人： Marina V. Plat ,  Christopher F. Lyons

IPC分类号： G03D500

CPC分类号： G03F7/3021 ,  G03D5/04

摘要： A resist developing method and apparatus for developing resist formed on a semiconductor wafer includes a rotating platform for supporting the wafer and a nozzle for applying developer to the resist. The nozzle is situated above the wafer and is positioned to be offset from an axis of rotation of the wafer during application of the developer to the resist. During application of the developer, the wafer is rotated at a rotational speed which allows the developer to remain on the wafer without flowing past the semiconductor edges. The developer is preferably applied for a time period less than or equal to 2 seconds.

摘要翻译： 用于在半导体晶片上形成的用于显影抗蚀剂的抗蚀剂显影方法和装置包括用于支撑晶片的旋转平台和用于将显影剂施加到抗蚀剂的喷嘴。 喷嘴位于晶片上方并且被定位成在将显影剂施加到抗蚀剂期间偏离晶片的旋转轴线。 在施加显影剂期间，晶片以允许显影剂保持在晶片上而不流过半导体边缘的转速旋转。 显影剂优选地施加小于或等于2秒的时间。

公开(公告)号：US06156480A

公开(公告)日：2000-12-05

申请号：US336455

申请日：1999-06-18

申请人： Christopher F. Lyons

发明人： Christopher F. Lyons

IPC分类号： G03F7/09 ,  G03F7/095 ,  G03F7/16 ,  G03F7/004

CPC分类号： G03F7/095 ,  G03F7/16 ,  G03F7/094

摘要： In one embodiment, the present invention relates to a method of forming a short wavelength thin photoresist coating having a low defect density by depositing sequentially at least two discrete ultra-thin photoresist layers to form the short wavelength thin photoresist coating, each ultra-thin photoresist layer independently having a thickness from about from about 200 .ANG. to about 2,500 .ANG., the short wavelength thin photoresist coating, having a thickness of about 5,000 .ANG. or less.

摘要翻译： 在一个实施方案中，本发明涉及通过依次沉积至少两个分立的超薄光致抗蚀剂层形成短波长薄光致抗蚀剂涂层，形成具有低缺陷密度的短波长薄光刻胶涂层的方法，每个超薄光致抗蚀剂 层，其厚度约为约200至约2500，短波长薄的光致抗蚀剂涂层具有约5,000或更小的厚度。

公开(公告)号：US06127089A

公开(公告)日：2000-10-03

申请号：US143105

申请日：1998-08-28

申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Uzodinma Okoroanyanwu

发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Uzodinma Okoroanyanwu

IPC分类号： G03F7/075 ,  H01L21/311 ,  H01L21/768 ,  G03C1/76

CPC分类号： H01L21/7681 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  G03F7/075

摘要： A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is a convertible layer that upon exposure to the plasma etch that etches the low k dielectric material, converts the silicon-rich imageble layer into a mask layer containing silicon dioxide, for example. The low k dielectric material is protected from further etching by the mask thus created.

摘要翻译： 一种镶嵌结构及其在低k电介质材料中的制造方法采用其中提供镶嵌图案的可成像层。 可成像层是可转换层，其在暴露于蚀刻低k介电材料的等离子体蚀刻时，例如将富含硅的图像层转换成含有二氧化硅的掩模层。 通过由此产生的掩模来保护低k电介质材料免于进一步蚀刻。

公开(公告)号：US6103611A

公开(公告)日：2000-08-15

申请号：US993830

申请日：1997-12-18

申请人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

发明人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/3065

CPC分类号： H01L21/31116

摘要： Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

摘要翻译： 提供了在半导体器件内形成间隔物期间增加工艺控制的方法和装置。 这些方法和布置包括使用非功能或虚拟线，区域和/或图案来创建导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

公开(公告)号：US6087271A

公开(公告)日：2000-07-11

申请号：US993869

申请日：1997-12-18

申请人： William G. En ,  Minh Van Ngo ,  Olov B. Karlsson ,  Christopher F. Lyons ,  Maria Chow Chan

发明人： William G. En ,  Minh Van Ngo ,  Olov B. Karlsson ,  Christopher F. Lyons ,  Maria Chow Chan

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/336 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L21/31116 ,  H01L29/6656 ,  H01L21/0276 ,  H01L29/66545

摘要： A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate following at least one etch back process associated with a spacer formation and/or subsequent resistor protect etching process or processes. The method eliminates the need to use HF acid in the stripping process by substantially reducing the thickness of the BARC during each of the etching back processes, such that, only a thin layer of BARC material remains that can be easily removed with phosphoric acid.

摘要翻译： 提供了一种用于在与间隔物形成和/或随后的电阻器保护蚀刻工艺或工艺相关联的至少一个回蚀工艺之后从晶体管栅极去除底部抗反射涂层（BARC）的方法。 该方法消除了在剥离过程中通过在每次蚀刻回加工过程中通过显着降低BARC的厚度而需要使用HF酸，使得仅剩下可以用磷酸容易地除去的薄的BARC材料层。

公开(公告)号：US06074927A

公开(公告)日：2000-06-13

申请号：US87662

申请日：1998-06-01

申请人： Nick Kepler ,  Basab Bandyopadhyay ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Nick Kepler ,  Basab Bandyopadhyay ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop over the pad oxide layer is removed by anisotropic etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. The portion of the polish stop remaining in the trench and on the oxide liner at the trench edges serves as a protective spacer, protecting the field oxide from erosion during subsequent processing steps.

摘要翻译： 形成浅沟槽隔离结构，其使得能够在沟槽边缘处生长高质量的栅极氧化物，并且保护场氧化物在后栅极处理（例如在局部互连蚀刻期间）中的气蚀，从而允许形成高质量 植入路口。 实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。 在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面中生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上的沟槽中。 然后将抛光停止层掩蔽到沟槽边缘，并且沟槽中的抛光停止点被各向异性地蚀刻，以去除沟槽底部的抛光停止部，留下覆盖氧化物衬垫上的沟槽的侧表面和边缘的部分 。 然后用绝缘材料填充沟槽，使绝缘材料平坦化，并通过各向异性蚀刻去除衬垫氧化物层上的抛光剂停止。 因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。 保留在沟槽中的抛光停止部分和在沟槽边缘处的氧化物衬垫上的部分用作保护间隔物，在随后的处理步骤期间保护场氧化物免受侵蚀。

公开(公告)号：US6057080A

公开(公告)日：2000-05-02

申请号：US987073

申请日：1997-12-09

申请人： William R. Brunsvold ,  George J. Hefferon ,  Christopher F. Lyons ,  Wayne M. Moreau ,  Robert L. Wood

发明人： William R. Brunsvold ,  George J. Hefferon ,  Christopher F. Lyons ,  Wayne M. Moreau ,  Robert L. Wood

IPC分类号： G03F7/11 ,  C08L27/12 ,  G03F7/00 ,  G03F7/09 ,  H01L21/027 ,  H01L21/30

CPC分类号： G03F7/091 ,  G03F7/092

摘要： Enhanced fidelity of pattern transfer of aqueous developable photoresist compositions is achieved with top antireflective coatings which are fluorine-containing and have a refractive index approximately equal to the square root of the underlying photoresist and which are removable in the developer for the photoresist.

摘要翻译： 水性可显影光致抗蚀剂组合物的图案转印的增强的保真度是通过含氟的顶部抗反射涂层实现的，其折射率近似等于下面的光致抗蚀剂的平方根，并且可在光致抗蚀剂的显影剂中除去。