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173 条记录 (耗时 0.048 秒)

    Write data mask method and system
    102.
    发明申请
    Write data mask method and system 有权
    写数据掩码的方法和系统

    公开(公告)号：US20070101073A1

    公开(公告)日：2007-05-03

    申请号：US11359809

    申请日：2006-02-22

    申请人： Joseph Macri ,  Stephen Morein ,  Ming-Ju Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Ming-Ju Lee ,  Lin Chen

    IPC分类号： G06F13/00

    CPC分类号： G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

    摘要： A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

    摘要翻译： 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。

    Communicating client phase information in an IO system
    103.
    发明申请
    Communicating client phase information in an IO system 有权
    在IO系统中沟通客户端阶段信息

    公开(公告)号：US20070067661A1

    公开(公告)日：2007-03-22

    申请号：US11231193

    申请日：2005-09-19

    申请人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

    发明人： Joseph Macri ,  Stephen Morein ,  Claude Gauthier ,  Ming-Ju Lee ,  Lin Chen

    IPC分类号： G06F1/04

    CPC分类号： G06F1/04 ,  G06F1/10 ,  H04L7/0012 ,  H04L7/033

    摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

    摘要翻译： 描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。 实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。 数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。 该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。 客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间传送的。

    Bit-deskewing IO method and system
    104.
    发明申请
    Bit-deskewing IO method and system 有权
    位偏移IO方法和系统

    公开(公告)号：US20070036020A1

    公开(公告)日：2007-02-15

    申请号：US11195082

    申请日：2005-08-01

    申请人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji M.K. ,  Gin Yee ,  Joseph Macri

    发明人： Edward Lee ,  Arvind Bomdica ,  Lin Chen ,  Claude Gauthier ,  Sam Huynh ,  Hiok-Tiaq Ng ,  John Ling ,  Jennifer Ho ,  Siji M.K. ,  Gin Yee ,  Joseph Macri

    IPC分类号： G11C8/00

    CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0805 ,  H04L7/0004 ,  H04L7/0037 ,  H04L7/0337

    摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.

    摘要翻译： 描述了用于位移校正的IO方法和系统。 实施例包括具有在其间传送数据的多个组件的计算机系统。 在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。 接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。 接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪 系统运行期间的正向选通采样时钟。

    Integrated converter having three-phase power factor correction
    105.
    发明授权
    Integrated converter having three-phase power factor correction 有权
    具有三相功率因数校正的集成转换器

    公开(公告)号：US07005759B2

    公开(公告)日：2006-02-28

    申请号：US10778622

    申请日：2004-02-12

    申请人： Jianping Ying ,  Jingtao Tan ,  Lin Chen ,  Raymond Lee

    发明人： Jianping Ying ,  Jingtao Tan ,  Lin Chen ,  Raymond Lee

    IPC分类号： H02J7/00

    CPC分类号： H02M1/4216 ,  H02J9/061 ,  H02J9/062 ,  H02M1/4225 ,  Y02B70/126 ,  Y02P80/112 ,  Y10T307/615 ,  Y10T307/625

    摘要： An integrated converter is provided. The integrated converter includes an AC/DC converter electrically connected to a three-phase power supply for converting an alternating current into a first direct current and achieving the object of the power factor correction; and a DC/DC converter electrically connected to the AC/DC converter for converting the first direct current into a second direct current, wherein while the AC power supply is electricity-drop, the controlling switch is turned on by the integrated converter and the integrated converter is switched from an AC/DC working mode to a DC/DC working mode, and while the AC power supply is restored to normal, the controlling switch is turned off by the integrated converter and the integrated converter is switched from said DC/DC working mode to the AC/DC working mode.

    摘要翻译： 提供集成转换器。 集成转换器包括电连接到三相电源的AC / DC转换器，用于将交流电转换成第一直流电并实现功率因数校正的目的; 以及DC / DC转换器，其电连接到所述AC / DC转换器，用于将所述第一直流电转换为第二直流电，其中当所述AC电源为电力下降时，所述控制开关由所述集成转换器接通， 转换器从AC / DC工作模式切换到DC / DC工作模式，当AC电源恢复正常时，控制开关由集成转换器关闭，集成转换器从所述DC / DC 工作模式到AC / DC工作模式。

    System for low miss rate replacement of texture cache lines
    106.
    发明授权
    System for low miss rate replacement of texture cache lines 有权
    低质量更新纹理缓存线路的系统

    公开(公告)号：US06590579B1

    公开(公告)日：2003-07-08

    申请号：US09664988

    申请日：2000-09-18

    申请人： Zhou Hong ,  Konstantine Iourcha ,  Lin Chen

    发明人： Zhou Hong ,  Konstantine Iourcha ,  Lin Chen

    IPC分类号： G06T1140

    CPC分类号： G06T15/04 ,  G06T11/40

    摘要： A system and method is provided for mipmap texturing in which texture tiles are mapped into sets of a set-associative texture cache for use in displaying a graphic primitive. When a miss occurs, a new texture tile is called from main memory to replace a texture tile which is not shared between the segment being traversed and the next segment to be traversed and which is the “least recently used”. This is accomplished by maintaining a record for each cache line describing the texture tile it contains and replacing the texture tile which is the “least likely to be reused”.

    摘要翻译： 提供了一种用于mipmap纹理的系统和方法，其中纹理贴图被映射到用于显示图形原语的组关联纹理缓存的集合中。 当出现未命中时，将从主存储器中调用新的纹理贴片，以替换未被遍历的段和要遍历的下一个段之间共享的纹理块，以及“最近最少使用的”。 这是通过维护描述其包含的纹理图块的每个高速缓存行的记录来实现的，并且替换“最不可能被重用”的纹理图块。

    Program flow control for multiple divergent SIMD threads using a minimum resume counter
    109.
    发明授权
    Program flow control for multiple divergent SIMD threads using a minimum resume counter 有权
    使用最小恢复计数器对多个发散SIMD线程进行程序流控制

    公开(公告)号：US08832417B2

    公开(公告)日：2014-09-09

    申请号：US13227274

    申请日：2011-09-07

    申请人： Lin Chen ,  David Rigel Garcia Garcia ,  Andrew E. Gruber ,  Guofang Jiao

    发明人： Lin Chen ,  David Rigel Garcia Garcia ,  Andrew E. Gruber ,  Guofang Jiao

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3887 ,  G06F9/322 ,  G06F9/3851

    摘要： This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction identified by a program counter value stored in a program counter register. The control flow instruction may include a target value indicative of a target program counter value for the control flow instruction. The control flow unit may select one of the target program counter value and a minimum resume counter value as a value to load into the program counter register. The minimum resume counter value may be indicative of a smallest resume counter value from a set of one or more resume counter values associated with one or more inactive threads. Each of the one or more resume counter values may be indicative of a program counter value at which a respective inactive thread should be activated.

    摘要翻译： 本公开描述了用于处理多线程处理系统中的发散线程状况的技术。 在一些示例中，控制流程单元可以获得由存储在程序计数器寄存器中的程序计数器值所标识的控制流程指令。 控制流程指令可以包括指示控制流程指令的目标程序计数器值的目标值。 控制流程单元可以选择目标程序计数器值和最小恢复计数器值之一作为加载到程序计数器寄存器中的值。 最小恢复计数器值可以指示与一个或多个非活动线程相关联的一个或多个恢复计数器值的集合中的最小恢复计数器值。 一个或多个恢复计数器值中的每一个可以指示应该激活相应的非活动线程的程序计数器值。