公开(公告)号：US09575125B1

公开(公告)日：2017-02-21

申请号：US14049543

申请日：2013-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  William Meadows

IPC: G01R31/3193 ,  G11C29/10

CPC classification number: G01R31/3193 ,  G01R31/31718 ,  G11C29/10 ,  G11C29/42 ,  G11C29/52

Abstract: In some examples, a memory device generates and exposes parity/difference information to a test system to reduce overall test time. The parity/difference information may be generated based on parity bits read from the memory device and parity bits produced from data bits stored in the memory device. In some cases, the parity/difference information may be compared to an expected parity/difference to determine a number of correctable errors which occurred during testing, while the data bits may be compared to expected data to determine a number of uncorrectable errors which occurred during testing.

Abstract translation: 在一些示例中，存储器件生成并将奇偶校验/差异信息暴露给测试系统以减少总体测试时间。 可以基于从存储器件读取的奇偶校验位和从存储在存储器件中的数据位产生的校验位来生成校验/差分信息。 在某些情况下，可以将奇偶校验/差分信息与期望的奇偶校验/差异进行比较，以确定在测试期间发生的可校正错误的数量，同时可将数据比特与期望数据进行比较，以确定在期间发生的不可校正错误的数量 测试。

公开(公告)号：US09530476B2

公开(公告)日：2016-12-27

申请号：US15143820

申请日：2016-05-02

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Chitra K. Subramanian

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: In some examples, a memory device may be configured to read or write multiple bit cells as part of the same operation. In some cases, the tunnel junctions forming the bit cells may be arranged to utilize shared read/write circuitry. For instance, the tunnel junctions may be arranged such that both tunnel junctions may be written using the same write voltages. In some cases, the bit cells may be configured such that each bit cell is driven to the same state, while in other cases, select bit cells may be driven high, while others are driven low.

公开(公告)号：US09529726B2

公开(公告)日：2016-12-27

申请号：US14155816

申请日：2014-01-15

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F12/08

CPC classification number: G06F11/1096 ,  G06F11/1064 ,  G06F12/0882 ,  G06F2211/109 ,  G06F2212/652 ,  G11C14/0036

Abstract: In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row.

Abstract translation: 在一些示例中，存储器设备被配置为响应于接收到激活命令而将内部页面大小的页面加载到高速缓存中，并且响应于接收到预充电命令而将内部页面大小的多页写入存储器阵列。 在一些实现中，存储器阵列被布置成在单个物理行中存储内部页面大小的多个页面。

公开(公告)号：US20160307615A1

公开(公告)日：2016-10-20

申请号：US15193010

申请日：2016-06-25

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

Abstract translation: 存储器单元的自参考读取包括首先在存储器单元上施加读取电压以产生采样电压。 在施加读取电压之后，将写入电流施加到存储器单元以将第一状态写入存储单元。 在施加写入电流之后，读取电压被重新应用于存储器单元。 在重新施加读取电压的同时施加偏置电流，并将得到的评估电压与读取电压重新应用偏移电流相比较，以确定存储单元的状态。

公开(公告)号：US20160254040A1

公开(公告)日：2016-09-01

申请号：US15149401

申请日：2016-05-09

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Abstract translation: 升压的电源电压发生器被选择性地激活和去激活，以允许以稳定的升压电压来执行对升压电压的变化敏感的操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。 这样的技术包括当停用时存储对应于电压发生器的状态信息，其中在重新激活电压发生器时使用存储的状态信息。 存储状态信息可以包括提供给电压发生器的时钟信号的状态。

公开(公告)号：US09311980B1

公开(公告)日：2016-04-12

申请号：US14052223

申请日：2013-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre ,  Halbert S. Lin

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C8/08 ,  G11C11/1657 ,  G11C11/1693 ,  G11C11/1697

Abstract: A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line voltages to be performed with a stable word line voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner.

Abstract translation: 字线电源电压发生器被选择性地激活和去激活以允许以稳定的字线电压执行对字线电压变化敏感的内部存储器操作。 还公开了用于停用和重新激活电压发生器的技术，其使得能够从停用中更快速地恢复，使得可以更快地开始后续操作。

公开(公告)号：US20160099040A1

公开(公告)日：2016-04-07

申请号：US14970564

申请日：2015-12-16

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.

公开(公告)号：US20160099037A1

公开(公告)日：2016-04-07

申请号：US14727965

申请日：2015-06-02

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Chitra K. Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

Abstract: In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.

Abstract translation: 在一些示例中，存储器件可以被配置为利用由两个或更多个隧道结形成的差分位单元。 在一些情况下，形成差分位单元的隧道结可以被布置为利用共享读取电路来减少器件失配。 例如，与隧道结相关联的读取操作可以被时间复用，使得相同的前置放大器电路可以感测代表隧道结的电压。

公开(公告)号：US20160093354A1

公开(公告)日：2016-03-31

申请号：US14502287

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G11C11/16 ,  G06F11/08

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。

公开(公告)号：US20160042780A1

公开(公告)日：2016-02-11

申请号：US14887426

申请日：2015-10-20

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.