中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

154 records (took 0.023 seconds)

    Methods of forming ruthenium conductive structures in a metallization layer
    101.
    发明授权
    Methods of forming ruthenium conductive structures in a metallization layer 有权
    在金属化层中形成钌导电结构的方法

    公开(公告)号：US09589836B1

    公开(公告)日：2017-03-07

    申请号：US15067365

    申请日：2016-03-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Hoon Kim

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285

    CPC classification number: H01L21/76843 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329

    Abstract: One illustrative method disclosed herein includes, among other things, forming a first conductive structure and a second conductive structure that is conductively coupled to the first conductive structure. In this example, forming the second conductive structure includes forming a ruthenium cap layer on and in contact with an upper surface of the first conductive structure, with the ruthenium cap layer in position, forming a liner layer comprising manganese on and in contact with at least the surfaces of the second layer of insulating material, wherein an upper surface of the ruthenium cap layer is substantially free of the liner layer, and forming a bulk ruthenium material on and in contact with the liner layer, wherein a bottom surface of the bulk ruthenium material contacts the upper surface of the ruthenium cap layer.

    Abstract translation: 本文公开的一种说明性方法尤其包括形成导电耦合到第一导电结构的第一导电结构和第二导电结构。 在该实施例中，形成第二导电结构包括在第一导电结构的上表面上形成钌帽层，并将钌盖层置于适当位置，形成在至少与 所述第二绝缘材料层的表面，其中所述钌覆盖层的上表面基本上不含所述衬里层，并且在所述衬里层上形成和接触所述衬层，并且在所述衬底层中形成本体钌材料，其中所述本体钌的底表面 材料接触钌盖层的上表面。

    Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices
    102.
    发明授权
    Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices 有权
    使用替代栅极技术形成用于半导体器件的栅极结构的方法和所得到的器件

    公开(公告)号：US09437711B2

    公开(公告)日：2016-09-06

    申请号：US14081019

    申请日：2013-11-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Xunyuan Zhang

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the H-terminated silicon surface, forming a high-k layer of insulating material within the replacement gate cavity above the H-terminated silicon surface and laterally between first spaced-apart portions of the sacrificial material layer, and forming a work-function adjusting material layer in the gate cavity, wherein the work-function adjusting material layer has a substantially planar upper surface that extends between second spaced-apart portions of the sacrificial material layer formed on the sidewall spacers.

    Abstract translation: 本文公开的一种方法包括在衬底的暴露表面上执行处理操作以形成H端接的硅表面，在置换栅腔内选择性地形成牺牲材料层，但不在H端接 硅表面，在H端接的硅表面上方的置换栅腔内形成高k层绝缘材料，并在牺牲材料层的第一间隔开的部分之间横向地形成绝缘材料的高k层，并在栅极中形成功函数调节材料层 空腔，其中所述功函调整材料层具有在形成在所述侧壁间隔物上的所述牺牲材料层的第二间隔开的部分之间延伸的基本平坦的上表面。

    Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure
    103.
    发明授权
    Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure 有权
    形成包括凹陷接触结构的半导体器件的V0结构的方法

    公开(公告)号：US09412660B1

    公开(公告)日：2016-08-09

    申请号：US14732078

    申请日：2015-06-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Xunyuan Zhang

    IPC: H01L21/768 ,  H01L29/417 ,  H01L21/8234

    CPC classification number: H01L21/76897 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66568

    Abstract: One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, recessing the source/drain contact structure to define a source/drain contact etch cavity and depositing a conformal second layer of insulating material above a first layer of insulating material and in the source/drain contact etch cavity. The method also includes forming a third layer of insulating material above the conformal second layer of insulating material, forming an opening in the conformal second layer of insulating material and forming a V0 via that is conductively coupled to the exposed portion of the recessed source/drain contact structure.

    Abstract translation: 本文中公开的一种说明性方法包括在两个间隔开的晶体管栅极结构之间形成源极/漏极接触结构，使源极/漏极接触结构凹陷以限定源极/漏极接触蚀刻腔并沉积第 绝缘材料在第一绝缘材料层上方和源/漏接触蚀刻腔中。 该方法还包括在第二绝缘材料层之上形成第三层绝缘材料，在第二绝缘材料层上形成一个开口，并形成一个V0通孔，导电耦合到凹陷源/漏极的露出部分 接触结构。

    METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER
    105.
    发明申请
    METHODS OF FORMING AN IMPROVED VIA TO CONTACT INTERFACE BY SELECTIVE FORMATION OF A METAL SILICIDE CAPPING LAYER 有权
    通过选择性形成金属硅化物覆盖层来形成接触界面的方法

    公开(公告)号：US20160126135A1

    公开(公告)日：2016-05-05

    申请号：US14526729

    申请日：2014-10-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Tibor Bolom ,  Errol Todd Ryan

    IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

    CPC classification number: H01L21/76883 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

    Abstract translation: 本文公开的一种说明性方法包括在至少一层绝缘材料中形成开口，从而暴露至少一部分导电接触，进行选择性金属硅化物形成工艺以选择性地形成金属硅化物层 在所述开口中和在所述导电接触件上，在所述选择性形成的金属硅化物层上方沉积至少一种导电材料，以便过度填充所述开口，并进行至少一个平坦化处理，以便去除多余的材料，从而限定导电通孔 其位于开口中并且导电地耦合到选择性形成的金属硅化物层和导电接触。

    SEMICONDUCTOR DEVICE WITH LOW-K SPACERS
    107.
    发明申请
    SEMICONDUCTOR DEVICE WITH LOW-K SPACERS 有权
    具有低K间隔的半导体器件

    公开(公告)号：US20150255561A1

    公开(公告)日：2015-09-10

    申请号：US14711196

    申请日：2015-05-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Xunyuan Zhang

    IPC: H01L29/49 ,  H01L29/78

    CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

    Abstract: One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

    Abstract translation: 本文公开的一种方法包括形成邻近牺牲栅极结构的至少一个牺牲侧壁间隔物，所述牺牲栅极结构形成在半导体衬底上方，去除牺牲栅极结构的至少一部分，从而限定由牺牲隔离物横向限定的栅极腔， 在栅极腔中形成替代栅极结构，去除牺牲隔离物，从而限定邻近置换栅极结构的间隔空腔，并在间隔空腔中形成低k隔离物。 本文公开的新型器件包括位于半导体衬底上方的栅极结构，其中栅绝缘层具有相对于衬底的上表面基本上垂直取向的两个直立部分。 该装置还包括邻近栅极绝缘层的垂直取向的竖立部分的低k侧壁间隔件。

    Method and device for self-aligned contact on a non-recessed metal gate
    109.
    发明授权
    Method and device for self-aligned contact on a non-recessed metal gate 有权
    在非凹槽金属门上进行自对准接触的方法和装置

    公开(公告)号：US09076816B2

    公开(公告)日：2015-07-07

    申请号：US14080842

    申请日：2013-11-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Xiuyu Cai ,  Hoon Kim

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

    CPC classification number: H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/6653 ,  H01L29/78

    Abstract: A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.

    Abstract translation: 公开了一种用于形成展现出接触到栅极短路故障的可能性降低的自对准接触（SAC）的方法以及所得到的器件。 实施例可以包括在衬底上形成具有相对侧面的间隔物的替换金属栅极，在替代金属栅极的外边缘上在间隔物的上表面中形成凹部，并在该金属栅极上形成氮化铝（AlN） 金属门和凹槽。

    Selective growth of a work-function metal in a replacement metal gate of a semiconductor device
    110.
    发明授权
    Selective growth of a work-function metal in a replacement metal gate of a semiconductor device 有权
    在半导体器件的替换金属栅中选择性地生长功函数金属

    公开(公告)号：US09018711B1

    公开(公告)日：2015-04-28

    申请号：US14056144

    申请日：2013-10-17

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Hoon Kim ,  Xunyuan Zhang

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092

    CPC classification number: H01L27/0924 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517

    Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

    Abstract translation: 公开了形成半导体器件的替代金属栅极（RMG）的方法。 具体地提供了在衬底上形成的p沟道场效应晶体管（p-FET）和n沟道场效应晶体管（n-FET），其中形成有凹部的p-FET和n-FET， 高k层和在每个凹槽内形成的阻挡层，选择性地生长在n-FET的凹槽内的功函数金属（WFM），其中高k层，势垒层和WFM各自凹入到期望的 在凹部内的高度，以及形成在每个凹部内的金属材料（例如，钨）。 通过在该方法中较早提供WFM倒角，减少了掩模材料填充到每个浇口凹槽中的风险。 此外，选择性WFM生长改善了金属材料的填充，这降低了器件中的栅极电阻。

Patent Agency Ranking