公开(公告)号：US20250107174A1

公开(公告)日：2025-03-27

申请号：US18977288

申请日：2024-12-11

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Stephen M. CEA ,  Ashish AGRAWAL ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US20240234422A1

公开(公告)日：2024-07-11

申请号：US18614290

申请日：2024-03-22

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Anh PHAN ,  Nicole K. THOMAS ,  Urusa ALAAN ,  Seung Hoon SUNG ,  Christopher M. NEUMANN ,  Willy RACHMADY ,  Patrick MORROW ,  Hui Jae YOO ,  Richard E. SCHENKER ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ehren MANNEBACH

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7853 ,  H10B12/056

Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US20240186398A1

公开(公告)日：2024-06-06

申请号：US18073213

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Patrick MORROW ,  Jack T. KAVALIEROS ,  Justin WEBER ,  Salim BERRADA

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4991 ,  H01L21/28123 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.

公开(公告)号：US20240145549A1

公开(公告)日：2024-05-02

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20240047559A1

公开(公告)日：2024-02-08

申请号：US18381887

申请日：2023-10-19

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US20230200043A1

公开(公告)日：2023-06-22

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Julie ROLLINS ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230170350A1

公开(公告)日：2023-06-01

申请号：US18095973

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Aaron LILAK ,  Patrick MORROW ,  Anh PHAN ,  Ehren MANNEBACH ,  Jack T. KAVALIEROS

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823481 ,  H01L29/66545 ,  H01L21/823431

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US20230006067A1

公开(公告)日：2023-01-05

申请号：US17940949

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Sean MA ,  Abhishek SHARMA ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Van H. LE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L27/12

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US20220310818A1

公开(公告)日：2022-09-29

申请号：US17211751

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Seung Hoon SUNG ,  Tristan TRONIC ,  Szuya S. LIAO ,  Jack T. KAVALIEROS

IPC: H01L29/49 ,  H01L23/535 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238

Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

公开(公告)号：US20220208778A1

公开(公告)日：2022-06-30

申请号：US17134281

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Nazila HARATIPOUR ,  Sou-Chi CHANG ,  Shriram SHIVARAMAN ,  Jason PECK ,  Uygar E. AVCI ,  Jack T. KAVALIEROS

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L27/11507 ,  G11C7/18 ,  G11C8/14 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

Abstract: A memory device comprises a series of alternating plate lines and an insulating material over a substrate. Two or more ferroelectric capacitors are through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel wordlines is along a second direction orthogonal to the first direction over the two or more ferroelectric capacitors. An access transistor is located over and controls the two or more ferroelectric capacitors, the access transistor incorporating a first one of the bitlines and a first one of the wordlines. The bitline comprise a first source/drain of a source/drain pair, and a second source/drain is aligned, and in contact, with a top one of the two or more ferroelectric capacitors, and the first wordline forms a gate of the access transistor.