公开(公告)号：US20240172408A1

公开(公告)日：2024-05-23

申请号：US17991243

申请日：2022-11-21

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Ruilong Xie ,  Junli Wang ,  Carl Radens

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78

CPC classification number: H10B10/125 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B10/12 ,  H01L29/66795 ,  H01L29/785

Abstract: A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

公开(公告)号：US20240155822A1

公开(公告)日：2024-05-09

申请号：US18053451

申请日：2022-11-08

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruilong Xie ,  Albert M. Chu ,  Carl Radens

IPC: H01L27/11 ,  H01L23/48

CPC classification number: H01L27/1104 ,  H01L23/481

Abstract: A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

公开(公告)号：US20240088146A1

公开(公告)日：2024-03-14

申请号：US17931319

申请日：2022-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M. Chu ,  Carl Radens ,  Brent A. Anderson

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region. A middle section contact is located in the middle gate cut region.

公开(公告)号：US20240079316A1

公开(公告)日：2024-03-07

申请号：US17903644

申请日：2022-09-06

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Albert M. Chu ,  Carl Radens ,  Brent A. Anderson

IPC: H01L23/522 ,  H01L21/74 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/743 ,  H01L23/481 ,  H01L23/5286

Abstract: A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

公开(公告)号：US11791199B2

公开(公告)日：2023-10-17

申请号：US17406351

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Carl Radens

IPC: H01L21/762 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L27/088

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66545

Abstract: An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.

公开(公告)号：US11645206B2

公开(公告)日：2023-05-09

申请号：US17472764

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Ahmet Serkan Ozcan ,  Tomasz Kornuta ,  Carl Radens ,  Nicolas Antoine

IPC: G06F16/00 ,  G06F16/2453 ,  G06F12/02 ,  G06F12/0817 ,  G06F16/33 ,  G06N3/063 ,  G11C11/4076 ,  G11C11/4093 ,  G06F16/2458 ,  G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0824 ,  G06F12/0246 ,  G06F16/3347 ,  G06N3/063 ,  G11C11/4076 ,  G11C11/4093 ,  G06F3/067 ,  G06F12/06 ,  G06F16/2458 ,  G06F16/24545

Abstract: A method for using a distributed memory device in a memory augmented neural network system includes receiving, by a controller, an input query to access data stored in the distributed memory device, the distributed memory device comprising a plurality of memory banks. The method further includes determining, by the controller, a memory bank selector that identifies a memory bank from the distributed memory device for memory access, wherein the memory bank selector is determined based on a type of workload associated with the input query. The method further includes computing, by the controller and by using content based access, a memory address in the identified memory bank. The method further includes generating, by the controller, an output in response to the input query by accessing the memory address.

公开(公告)号：US20230133058A1

公开(公告)日：2023-05-04

申请号：US17453346

申请日：2021-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Kangguo Cheng ,  Carl Radens ,  Ruilong Xie

IPC: H01L45/00 ,  H01L27/24

Abstract: A structure including a bottom electrode on a substrate, a first side electrode vertically aligned above the bottom electrode, a set of alternating layers of insulator layers and conductive layers horizontally adjacent to the first side electrode, and a resistance switching material layer, the resistance switching material layer horizontally adjacent to a first side of the set of alternating layers. A method including forming a structure, the structure including alternating layers of insulator layers and conductive layers on a substrate, the substrate including a bottom electrode, removing a vertically aligned portion of the alternating layers forming a first trench, forming a first side electrode adjacent to the alternating layers in a portion of the first trench, removing another vertically aligned portion of the alternating layers forming a second trench, and forming a resistance switching material layer in the second trench.

公开(公告)号：US20230086033A1

公开(公告)日：2023-03-23

申请号：US17480531

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Julien Frougier ,  Veeraraghavan S. Basker ,  Lawrence A. Clevenger ,  Nicolas Loubet ,  Dechao Guo ,  Kisik Choi ,  Kangguo Cheng ,  Carl Radens

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/768 ,  H01L29/40

Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

公开(公告)号：US20220416161A1

公开(公告)日：2022-12-29

申请号：US17358223

申请日：2021-06-25

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Carl Radens ,  JUNTAO LI ,  Ruilong Xie ,  Praneet Adusumilli ,  Oscar van der Straten ,  Alexander Reznicek

IPC: H01L45/00

Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

公开(公告)号：US20220399493A1

公开(公告)日：2022-12-15

申请号：US17303836

申请日：2021-06-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Carl Radens ,  JUNTAO LI

IPC: H01L45/00

Abstract: A phase change memory (PCM) cell comprising a substrate a first electrode located on the substrate. A phase change material layer located adjacent to the first electrode, wherein a first side of the phase change material layer is in direct contact with the first electrode. A second electrode located adjacent to phase change material layer, wherein the second electrode is in direct contact with a second side of the phase change material layer, wherein the first side and the second side are different sides of the phase change material layer. An airgap is located directly above the phase change material layer, wherein the airgap provides space for the phase change material to expand or restrict.