公开(公告)号：US20050074009A1

公开(公告)日：2005-04-07

申请号：US10954475

申请日：2004-10-01

申请人： Tatsuo Kanetake ,  Kazuo Sugai ,  Takashi Kumagai

发明人： Tatsuo Kanetake ,  Kazuo Sugai ,  Takashi Kumagai

IPC分类号： H04L12/701 ,  H04L12/44 ,  H04L12/741 ,  H04L12/56

CPC分类号： H04L49/552 ,  H04L49/3009 ,  H04L49/354

摘要： The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.

摘要翻译： 本发明涉及一种分组传送单元，其包括搜索密钥存储器，其存储用于分组的传送目的地的搜索关键字和从搜索关键字生成的验证信息，与存储在传送中的传送信息的存储位置相关联 信息存储器，其中传送信息获取单元通过使用基于标题信息生成的搜索关键字和从搜索关键字生成的验证信息来搜索搜索关键字存储器，当搜索关键字存储器 找到与搜索关键字相匹配的存储位置信息和存储在搜索关键字存储器中的验证信息，并且基于所获取的存储位置信息获取存储在传送信息存储器中的传送信息，并且其中传送单元基于所获取的传送 信息。

公开(公告)号：US06329693B1

公开(公告)日：2001-12-11

申请号：US09591088

申请日：2000-06-09

申请人： Takashi Kumagai

发明人： Takashi Kumagai

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  Y10S257/903

摘要： A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

摘要翻译： 半导体存储器件具有硅衬底10.第一嵌入层11在驱动晶体管30的漏极36所在的区域下方的区域中的p阱18之下的硅衬底10中形成。 第一嵌入层11与p阱18形成结。而且，第一嵌入层11形成在n阱16的下方并与n阱16接触。当驱动晶体管30的漏极36处于 3V的电压，α射线可以通过p阱18，第一埋入层11和硅衬底10.结果，电子 - 空穴对被切割。 由于存在由p阱18和第一嵌入层11形成的pn结，所以只有p阱18中的电子被吸引到漏极36。结果，漏极电压的下降 3V减少。 因此，设备结构使得很难破坏保留的数据。

公开(公告)号：US5875133A

公开(公告)日：1999-02-23

申请号：US809383

申请日：1997-06-19

申请人： Koji Miyashita ,  Takashi Kumagai ,  Yasunobu Tokuda

发明人： Koji Miyashita ,  Takashi Kumagai ,  Yasunobu Tokuda

IPC分类号： G11C8/08 ,  G11C8/14 ,  G11C16/04

CPC分类号： G11C8/14 ,  G11C8/08

摘要： A semiconductor memory device that steps up word lines, each of whose length is short enough to stay within one of the blocks that is formed by dividing a memory cell array into multiple blocks. The device includes multiple memory cells connected to pairs of bit lines and word lines at intersections of the pairs of bit lines and the word lines. Multiple memory cell array blocks are formed by dividing the region where the memory cells are arranged into blocks. A first step-up line is commonly used in stepping-up the word lines. A step-up circuit is constructed of a step-up capacitor, which is connected to the first step-up line and a switching transistor, which precharges the step-up capacitor. The semiconductor memory device also has a step-up control circuit that outputs a precharge control signal, which precharges the step-up capacitor by ON driving the switching transistor, and a step-up driving signal, which changes the potential of the negative terminal of the step-up capacitor of the step-up circuit. Further, a second step-up line is provided in each memory cell array block. During operation, a single memory cell array block is selected by a block selective circuit and a single word line is selected by row selective circuits. In this manner, the single selected word line within the single selected memory cell array block is stepped up by means of the first and second step-up lines.

摘要翻译： PCT No.PCT / JP96 / 02018 Sec。 371日期：1997年6月19日 102（e）日期1996年6月19日PCT PCT 1996年7月19日PCT公布。 出版物WO97 / 04458 日期1997年2月6日一种半导体存储器件，其加长字线，其长度足够短以保持在通过将存储器单元阵列分割成多个块而形成的块之一内。 该装置包括多个存储器单元，连接到位线对和字线对，位线对和字线对的交点处。 多个存储单元阵列块通过将存储单元排列成块的区域进行划分而形成。 第一个升压线通常用于加紧字线。 升压电路由与第一升压线连接的升压电容器和对升压电容器进行预充电的开关晶体管构成。 半导体存储器件还具有升压控制电路，其输出通过ON驱动开关晶体管对升压电容器进行预充电的预充电控制信号，以及升压驱动信号，其使负极端子的电位变化 升压电路的升压电容器。 此外，在每个存储单元阵列块中提供第二升压线。 在操作期间，通过块选择电路选择单个存储单元阵列块，并且通过行选择电路选择单个字线。 以这种方式，单个选择的存储单元阵列块内的单个选定字线通过第一和第二升压线被升高。

公开(公告)号：US5067007A

公开(公告)日：1991-11-19

申请号：US645357

申请日：1991-01-24

申请人： Kanji Otsuka ,  Masao Kato ,  Takashi Kumagai ,  Mitsuo Usami ,  Shigeo Kuroda ,  Kunizo Sahara ,  Takeo Yamada ,  Seiji Miyamoto ,  Yuuji Shirai ,  Takayuki Okinaga ,  Kazutoshi Kubo ,  Hiroshi Tachi ,  Masayuki Kawashima

发明人： Kanji Otsuka ,  Masao Kato ,  Takashi Kumagai ,  Mitsuo Usami ,  Shigeo Kuroda ,  Kunizo Sahara ,  Takeo Yamada ,  Seiji Miyamoto ,  Yuuji Shirai ,  Takayuki Okinaga ,  Kazutoshi Kubo ,  Hiroshi Tachi ,  Masayuki Kawashima

IPC分类号： H01L23/50 ,  H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34

CPC分类号： H01L23/49555 ,  H01L23/433 ,  H01L23/49579 ,  H01L23/49811 ,  H05K3/3426 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K2201/0308 ,  H05K2201/10318 ,  H05K2201/10681 ,  H05K2201/10704 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

摘要： Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.

摘要翻译： 随着制造高密度和小尺寸集成电路的趋势，已经尝试增加封装引脚的数量。 本发明提供了提高具有增加的引脚数的表面安装型封装的可靠性的技术。 也就是说，当封装被安装在布线基板上时，从轴向接收负载的引线销显示出小于接合部处的焊料的接合强度的弯曲强度。 为了实现该目的，引脚由具有大弹性的材料制成，例如纤维增强材料，变形假弹性材料，超高张力材料或耐热超高张力材料。

公开(公告)号：US4484080A

公开(公告)日：1984-11-20

申请号：US402411

申请日：1982-07-27

申请人： Takashi Kumagai

发明人： Takashi Kumagai

IPC分类号： G03B13/36 ,  G01B11/24 ,  G01B11/245 ,  G02B7/28 ,  G03B3/00 ,  G01N21/86

CPC分类号： G01B11/245

摘要： A detecting device comprising a projecting optical system for focusing the image of an object to be examined on a focusing glass, a plurality of photoelectric elements which can be set in proper positions on the focusing glass, circuits including level adjusting circuits and for converting outputs from the respective photoelectric elements to binary logical outputs and circuits for converting these binary logical inputs to octonary logical outputs so that the slightest variations of the shape and state of the object can be easily and accurately detected. The respective photoelectric elements can be moved out of the projecting light path as required. The projecting optical system consists of an objective lens system and a projecting lens system so that a magnified erecting image of the object can be obtained on the focusing glass.

摘要翻译： 一种检测装置，包括用于将待检查对象的图像聚焦在聚焦玻璃上的投影光学系统，可以设置在聚焦玻璃上的适当位置的多个光电元件，包括电平调节电路的电路， 各个光电元件到二进制逻辑输出和用于将这些二进制逻辑输入转换成八进制逻辑输出的电路，使得可以容易且精确地检测对象的形状和状态的最微小的变化。 各光电元件可根据需要移出投影光路。 投影光学系统由物镜系统和投影透镜系统组成，从而可以在聚焦玻璃上获得物体的放大的立体图像。

公开(公告)号：US09973733B2

公开(公告)日：2018-05-15

申请号：US13589845

申请日：2012-08-20

申请人： Takashi Kumagai ,  Izuru Tanaka

发明人： Takashi Kumagai ,  Izuru Tanaka

IPC分类号： G06F21/00 ,  H04N7/173 ,  G06Q20/08 ,  G06F21/10 ,  G06Q20/12 ,  G06Q20/32 ,  G06Q30/02 ,  G06Q30/06 ,  G11B27/034 ,  G11B27/11 ,  G11B27/34 ,  H04H60/21 ,  H04H60/27 ,  H04N21/2225 ,  H04N21/254 ,  H04N21/2543 ,  H04N21/61 ,  H04N21/854 ,  H04Q11/04

CPC分类号： H04N7/173 ,  G06F21/10 ,  G06Q20/085 ,  G06Q20/123 ,  G06Q20/32 ,  G06Q20/3221 ,  G06Q30/0283 ,  G06Q30/0601 ,  G06Q2220/12 ,  G11B27/034 ,  G11B27/11 ,  G11B27/34 ,  G11B2220/20 ,  G11B2220/2525 ,  G11B2220/41 ,  G11B2220/65 ,  H04H60/21 ,  H04H60/27 ,  H04N21/2225 ,  H04N21/254 ,  H04N21/2543 ,  H04N21/6125 ,  H04N21/6175 ,  H04N21/85403 ,  H04Q11/04 ,  H04Q2213/13093 ,  H04Q2213/13097 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13176 ,  H04Q2213/13204 ,  H04Q2213/13216 ,  H04Q2213/13299 ,  H04Q2213/13333 ,  H04Q2213/13376 ,  H04Q2213/13389 ,  H04Q2213/13399 ,  Y10S707/944 ,  Y10S707/99931 ,  Y10S707/99932 ,  Y10S707/99936 ,  Y10S707/99948

摘要： A communication system includes a terminal having a first storage section for storing a number of pieces of content information, a second storage section for storing a number of pieces of the content information, a storage control section for placing a content ID stored in the second storage section into purchase information for each terminal and stored in the second storage section, an access control section for controlling access to the content information corresponding to the content ID stored in the second storage section, and an accounting setting section for setting an amount of a fee to be imposed on the terminal in response to the purchase information.

公开(公告)号：US08345365B2

公开(公告)日：2013-01-01

申请号：US13358297

申请日：2012-01-25

申请人： Toshiyuki Arai ,  Takashi Kumagai ,  Hajime Inai ,  Hiroaki Sato ,  Fumitake Yodo ,  Masami Oyama

发明人： Toshiyuki Arai ,  Takashi Kumagai ,  Hajime Inai ,  Hiroaki Sato ,  Fumitake Yodo ,  Masami Oyama

IPC分类号： G11B5/00

CPC分类号： G11B31/00 ,  G11B20/00007 ,  G11B20/10527 ,  G11B27/005 ,  G11B27/034 ,  G11B27/105 ,  G11B27/11 ,  G11B27/329 ,  G11B27/34 ,  G11B2220/213 ,  G11B2220/2525 ,  G11B2220/2545 ,  G11B2220/2562 ,  H04R5/02

摘要： A processing unit performs a method including controlling a reading-out of data from a first storage medium at a predetermined read-out data rate to produce inputted data, and controlling a compression of the inputted data to produce first compressed data of a first compressed format. The method includes controlling a storage of the first compressed data in a second storage medium at a faster writing data rate than the predetermined read-out data rate, controlling a reading-out of second compressed data of a second compressed format from the second storage medium, and controlling a decompression of the second compressed data to produce decompressed data. The method also includes controlling simultaneously the storage of the first compressed data in the second storage medium, the reading-out of the second compressed data from the second storage medium, and audibly reproducing the decompressed data. The first compressed format is different from the second compressed format.

摘要翻译： 处理单元执行包括以预定的读出数据速率控制从第一存储介质读出数据以产生输入数据并且控制输入数据的压缩以产生第一压缩格式的第一压缩数据的方法 。 该方法包括以比预定读出数据速率更快的写入数据速率控制第二存储介质中的第一压缩数据的存储，控制从第二存储介质读出第二压缩格式的第二压缩数据 并且控制第二压缩数据的解压缩以产生解压缩数据。 该方法还包括同时控制第二存储介质中的第一压缩数据的存储，从第二存储介质读出第二压缩数据，以及可听再现解压缩的数据。 第一种压缩格式与第二种压缩格式不同。

公开(公告)号：US08249516B2

公开(公告)日：2012-08-21

申请号：US12681222

申请日：2008-08-29

申请人： Hideki Kumagai ,  Takashi Kumagai

发明人： Hideki Kumagai ,  Takashi Kumagai

IPC分类号： H04B17/00

CPC分类号： H04B1/12 ,  G01V3/12

摘要： An output signal SHS is secondarily amplified by a high-frequency amplifier AMP3 and an output signal SHR is secondarily amplified by an AMP4 for which high-frequency side amplitude reducing means is taken. In this case, the AMP4 has small gain of a high-frequency region and its output SHR-2 is reduced in amplitude. However, a high-frequency noise has a frequency higher than that of a carrier wave SH and the amplitude of a noise NzB becomes smaller. The other output signal SHS is directly amplified by the wideband amplifier AMP3. The width of an SHS-2 and the width of the SHR-2 are adjusted by amplitude adjusting means throughout the whole region and then mutually added by both signals addition amplifying means again so that the amplitude of the output signal SHS is adjusted to the SHR-2, and a predetermined threshold value is set to extract the noises.

摘要翻译： 输出信号SHS被高频放大器AMP3二次放大，并且输出信号SHR由被采用高频侧振幅降低装置的AMP4二次放大。 在这种情况下，AMP4具有高频区域的小增益，并且其输出SHR-2的振幅减小。 然而，高频噪声的频率高于载波SH的频率，并且噪声的振幅NzB变小。 另一个输出信号SHS由宽带放大器AMP3直接放大。 SHS-2的宽度和SHR-2的宽度通过振幅调整装置在整个区域中进行调整，然后由两个信号加法放大装置再次相加，使得输出信号SHS的振幅被调整到SHR -2，并且设置预定阈值以提取噪声。

公开(公告)号：US20120154539A1

公开(公告)日：2012-06-21

申请号：US13300254

申请日：2011-11-18

申请人： Tamotsu Hasegawa ,  Takashi Kumagai ,  Nobuyuki Ikeda

发明人： Tamotsu Hasegawa ,  Takashi Kumagai ,  Nobuyuki Ikeda

IPC分类号： H04N13/02

CPC分类号： H04N13/128 ,  H04N13/156 ,  H04N13/178 ,  H04N13/183

摘要： According to one embodiment, an image processing apparatus including a background image generator which generates a background image, a receiver which receives additional information, a depth memory which stores in advance a depth for each of types of the additional information, a depth decide module which determines a type of the additional information received by the receiver, and reads a depth which is associated with the determined type from the depth memory, a three-dimensional image generator which generates an object image based on the additional information, and generates a three-dimensional image based on the object image and the depth which is read by the depth decide module, an image composite module which generates a video signal by displaying the background image and displaying the three-dimensional image in front of the displayed background image, and an output module which outputs the video signal generated by the image composite module.

摘要翻译： 根据一个实施例，一种图像处理装置，包括产生背景图像的背景图像生成器，接收附加信息的接收器，预先存储每种附加信息的深度的深度存储器，深度决定模块， 确定由接收器接收的附加信息的类型，并且从深度存储器读取与所确定的类型相关联的深度，基于附加信息生成对象图像的三维图像生成器， 基于由深度决定模块读取的对象图像和深度的三维图像，通过显示背景图像并在显示的背景图像的前方显示三维图像来生成视频信号的图像合成模块，以及 输出模块，其输出由图像复合模块生成的视频信号。

公开(公告)号：US08197310B2

公开(公告)日：2012-06-12

申请号：US13273570

申请日：2011-10-14

申请人： Yukio Yamashiro ,  Hirokazu Hagiwara ,  Yoshifumi Morita ,  Takashi Kumagai

发明人： Yukio Yamashiro ,  Hirokazu Hagiwara ,  Yoshifumi Morita ,  Takashi Kumagai

IPC分类号： B24B55/06

CPC分类号： B23Q11/0042 ,  B23Q11/0046 ,  B24B55/102 ,  Y02P70/171

摘要： A dust box includes: an attachment portion configured to be attached to a dust-discharging nozzle extending from a housing of an electric tool; and a dust-collecting portion connected to the attachment portion and configured to store dust particles to be discharged from the nozzle. The dust-collecting portion mainly consists of a box which is made of synthetic resin and configured to be detachably connected to the attachment portion, and a paper bag received in the box and configured to store the dust particles to be discharged from the nozzle.

摘要翻译： 集尘盒包括：附接部，其构造成附接到从电动工具的壳体延伸的排尘喷嘴; 以及集尘部，其连接到所述安装部，并且构造成存储要从所述喷嘴排出的灰尘颗粒。 集尘部分主要由合成树脂制成的盒子构成，其可拆卸地连接到安装部分，纸箱容纳在盒子中，用于存储要从喷嘴排出的灰尘颗粒。