公开(公告)号：US11362018B2

公开(公告)日：2022-06-14

申请号：US16668296

申请日：2019-10-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Deepak C. Pandey ,  Haitao Liu ,  Chandra Mouli

IPC: H01L23/538 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: Apparatuses and methods are disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

公开(公告)号：US11309321B2

公开(公告)日：2022-04-19

申请号：US17107814

申请日：2020-11-30

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Chandra Mouli ,  Sergei Koveshnikov ,  Dimitrios Pavlopoulos ,  Guangyu Huang

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11582

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

公开(公告)号：US11302703B2

公开(公告)日：2022-04-12

申请号：US16803948

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  H01L27/07 ,  H01L27/11553 ,  H01L29/92 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20210408244A1

公开(公告)日：2021-12-30

申请号：US17468936

申请日：2021-09-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Chandra Mouli

IPC: H01L21/28 ,  G11C16/04 ,  H01L21/763

Abstract: Field-effect transistors, and methods of forming such field-effect transistors, including a gate dielectric overlying a semiconductor material, and a control gate overlying the gate dielectric, wherein the control gate includes an instance of a first polycrystalline silicon-containing material consisting essentially of polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material selected from a group consisting of polycrystalline silicon-germanium and polycrystalline silicon-germanium-carbon.

公开(公告)号：US20210257387A1

公开(公告)日：2021-08-19

申请号：US17308766

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20210050443A1

公开(公告)日：2021-02-18

申请号：US16542078

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L29/267 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.

公开(公告)号：US10388864B2

公开(公告)日：2019-08-20

申请号：US15684081

申请日：2017-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L45/00 ,  H01L29/78 ,  H01L29/267 ,  H01L21/02 ,  H01L27/115 ,  H01L29/12 ,  H01L29/786 ,  H01L23/535 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/10

Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.

公开(公告)号：US10381357B2

公开(公告)日：2019-08-13

申请号：US16043653

申请日：2018-07-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US10304518B2

公开(公告)日：2019-05-28

申请号：US15633595

申请日：2017-06-26

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Chandra Mouli ,  Haitao Liu

IPC: G11C11/419 ,  G11C11/408 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

公开(公告)号：US09953710B2

公开(公告)日：2018-04-24

申请号：US15583411

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66 ,  G11C16/14 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/792 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.