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    Controlling clock input buffers
    102.
    发明授权
    Controlling clock input buffers 有权
    控制时钟输入缓冲区

    公开(公告)号：US09577611B2

    公开(公告)日：2017-02-21

    申请号：US14448706

    申请日：2014-07-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Daniele Balluchi ,  Daniele Vimercati ,  Graziano Mirichigni

    IPC: G11C5/14 ,  H03K3/012 ,  G11C7/22 ,  G11C11/4072

    CPC classification number: H03K3/012 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4072

    Abstract: An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

    Abstract translation: 集成电路可以具有耦合到缓冲器（24）的时钟输入引脚。 缓冲器可以向诸如存储器的集成电路芯片提供时钟信号（28）。 为了节省电力，缓冲区掉电。 当准备使用时，缓冲区被快速备份。 在一个实施例中，响应于预定数量的时钟信号切换，缓冲器被自动加电。

    Providing power availability information to memory
    105.
    发明授权
    Providing power availability information to memory 有权
    向内存提供电源可用性信息

    公开(公告)号：US09343116B2

    公开(公告)日：2016-05-17

    申请号：US14288618

    申请日：2014-05-28

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Corrado Villa

    IPC: G11C5/14

    CPC classification number: G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

    Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

    Abstract translation: 本公开包括用于向存储器提供功率可用性信息的装置和方法。 许多实施例包括存储器和控制器。 控制器被配置为向存储器提供电力和电力可用性信息，并且存储器被配置为至少部分地基于电力可用性信息来确定是否调整其操作。

    Non-volatile memory circuit, system, and method
    107.
    发明授权
    Non-volatile memory circuit, system, and method 有权
    非易失性存储器电路，系统和方法

    公开(公告)号：US08825979B2

    公开(公告)日：2014-09-02

    申请号：US14034275

    申请日：2013-09-23

    Applicant: Micron Technology, Inc.

    Inventor： Daniele Balluchi ,  Graziano Mirichigni

    IPC: G06F12/00

    CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

    Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

    Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

    POST PACKAGE REPAIR RESOURCES FOR MEMORY DEVICES
    108.
    发明申请
    POST PACKAGE REPAIR RESOURCES FOR MEMORY DEVICES 有权

    公开(公告)号：US20250077348A1

    公开(公告)日：2025-03-06

    申请号：US18776730

    申请日：2024-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Antonino Capri' ,  Daniele Balluchi ,  Joseph M. McCrate ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin

    IPC: G06F11/10

    Abstract: A variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. The one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. Arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. Other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. Combinations of arrangements may be implemented. Additional apparatus, systems, and methods are disclosed.

    ROW ACTIVATION INDICATION REGISTERS
    109.
    发明申请
    ROW ACTIVATION INDICATION REGISTERS 有权

    公开(公告)号：US20250006248A1

    公开(公告)日：2025-01-02

    申请号：US18749370

    申请日：2024-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Antonino Caprì

    IPC: G11C11/408 ,  G11C11/4076

    Abstract: Methods, systems, and devices related to row activation indication registers are disclosed. A first register can be coupled to a memory device and configured to store an indication of a first number of bit locations of a row address corresponding to the memory device to use in association with optimization of a row precharge time (tRP) of the memory device. A second register can be coupled to the memory device and configured to store an indication of a second number of bit locations of the row address to use in association with optimization of a row address to column address delay (tRCD) of the memory device.

    Techniques for indicating row activation
    110.
    发明授权
    Techniques for indicating row activation 有权

    公开(公告)号：US12183421B2

    公开(公告)日：2024-12-31

    申请号：US18408228

    申请日：2024-01-09

    Applicant: Micron Technology, Inc.

    Inventor： Graziano Mirichigni ,  Efrem Bolandrina

    IPC: G11C7/10 ,  G11C8/18

    Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.

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