公开(公告)号：US09665462B2

公开(公告)日：2017-05-30

申请号：US14883377

申请日：2015-10-14

Applicant: Micron Technology, Inc.

Inventor： Suryanarayana Tatapudi ,  Sujeet Ayyapureddi

IPC: G11C5/06 ,  G06F11/34 ,  G11C8/10 ,  G11C8/06 ,  G06F11/30

CPC classification number: G06F1/3225 ,  G06F1/3296 ,  G06F11/348 ,  G06F13/1605 ,  G11C7/1057 ,  G11C7/1066 ,  G11C8/06 ,  G11C8/10 ,  G11C2207/2245 ,  G11C2207/2254

Abstract: An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command.

公开(公告)号：US09570201B2

公开(公告)日：2017-02-14

申请号：US15156165

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sujeet Ayyapureddi

IPC: G11C17/16 ,  G11C29/00

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C29/78 ,  G11C29/787 ,  G11C29/88

Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract translation: 公开了用于混合后包装修复的装置和方法。 一种这样的装置可以包括包括存储器单元和易失性存储器的封装。 易失性存储器可以被配置为存储对应于被认为是有缺陷的后封装的存储器单元的第一部分的有缺陷的地址数据。 该装置还可以包括解码器，其被配置为当与要访问的地址相对应的当前地址数据与存储在易失性存储器中的缺陷地址数据匹配时，选择存储器单元的第二部分而不是存储器单元的第一部分。 该装置还可以包括包装中的非易失性存储器。 该装置还可以包括封装中的映射逻辑电路。 映射逻辑电路可以被配置为在故障地址数据被存储到易失性存储器之后将替换地址数据编程到非易失性存储器。

公开(公告)号：US20160307647A1

公开(公告)日：2016-10-20

申请号：US15156165

申请日：2016-05-16

Applicant: Micron Technology, Inc.

Inventor： DONALD M. MORGAN ,  Sujeet Ayyapureddi

IPC: G11C29/00 ,  G11C17/16

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C29/78 ,  G11C29/787 ,  G11C29/88

Abstract: Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The volatile memory may be configured to store defective address data corresponding to a first portion of the memory cells that are deemed defective post-packaging. The apparatus may also include a decoder configured to select a second portion of the memory cells instead of the first portion of the memory cells when received current address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The apparatus may also include non-volatile memory in the package. The apparatus may also include a mapping logic circuit in the package. The mapping logic circuit may be configured to program the replacement address data to the non-volatile memory subsequent to the defective address data being stored to the volatile memory.

Abstract translation: 公开了用于混合后包装修复的装置和方法。 一种这样的装置可以包括包括存储器单元和易失性存储器的封装。 易失性存储器可以被配置为存储对应于被认为是有缺陷的后封装的存储器单元的第一部分的有缺陷的地址数据。 该装置还可以包括解码器，其被配置为当与要访问的地址相对应的当前地址数据与存储在易失性存储器中的缺陷地址数据匹配时，选择存储器单元的第二部分而不是存储器单元的第一部分。 该装置还可以包括包装中的非易失性存储器。 该装置还可以包括封装中的映射逻辑电路。 映射逻辑电路可以被配置为在存储到易失性存储器的缺陷地址数据之后将替换地址数据编程到非易失性存储器。

公开(公告)号：US20150302907A1

公开(公告)日：2015-10-22

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C8/06 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US20250165383A1

公开(公告)日：2025-05-22

申请号：US18920337

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G06F12/02

Abstract: A memory device stored data and associated metadata. During a read operation, memory receives a column address and decodes it into a column select value. Based on a range of values which contain that column select value, a block of metadata which includes the associated metadata is read. The memory subtracts a minimum value of the range of values from the column select value to determine a metadata location value. The metadata location value indicates a relative position of the associated metadata within the block of metadata, and the data and associated metadata are read out.

公开(公告)号：US20250110825A1

公开(公告)日：2025-04-03

申请号：US18747635

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi

IPC: G06F11/10

Abstract: Apparatuses, systems, and methods for read/modify/write single-pass metadata access operations. During a write a memory receives data bits and at least one metadata bit and a column address which includes column select bits and column sub-select bits. A column decoder selects a set of bit lines in an extra column plane based on the column select bits and a set of bits is read out. A subset of that set of bits is selected based on the column sub-select bits and overwritten with the at least one metadata bit. The modified set of bits is written back to the extra column plane.

公开(公告)号：US12248567B2

公开(公告)日：2025-03-11

申请号：US17940785

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Tamara Schmitz ,  Edmund Gieske ,  Nicolo Izzo ,  Markus H. Geiger

IPC: G06F21/55 ,  G06F21/54

Abstract: A system and method detect a row hammer attack on the memory media device and generates a hardware interrupt based on the detection of the row hammer attack. This row hammer interrupt is communicated to an operating system of a host computing device, which in turn performs an interrupt service routine including generating a command to perform a row hammer mitigation operation. This command is provided to the memory controller which performs the row hammer mitigation operation in response to the command such as activating victim row(s) of the memory media device or throttling data traffic to the memory media device.

公开(公告)号：US12230311B2

公开(公告)日：2025-02-18

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Cagdas Dirik ,  Robert M. Walker ,  Sujeet Ayyapureddi ,  Niccolo Izzo ,  Markus Geiger ,  Yang Lu ,  Ameen Akel ,  Elliott C. Cooper-Balis ,  Danilo Caraccio

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

公开(公告)号：US20240312553A1

公开(公告)日：2024-09-19

申请号：US18598832

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/52

CPC classification number: G11C29/52

Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.

公开(公告)号：US20240312547A1

公开(公告)日：2024-09-19

申请号：US18598937

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi

IPC: G11C29/18 ,  G11C29/42 ,  G11C29/44

CPC classification number: G11C29/18 ,  G11C29/42 ,  G11C29/44

Abstract: Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.