公开(公告)号：US20060252226A1

公开(公告)日：2006-11-09

申请号：US11485599

申请日：2006-07-12

申请人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zarchary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/76

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

公开(公告)号：US20060124936A1

公开(公告)日：2006-06-15

申请号：US10905002

申请日：2004-12-09

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L29/786 ,  H01L21/8242

CPC分类号： H01L29/78642 ,  H01L27/10864 ,  H01L27/1087

摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的键合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

公开(公告)号：US20050282393A1

公开(公告)日：2005-12-22

申请号：US10710061

申请日：2004-06-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl Radens

IPC分类号： H01L21/302 ,  H01L21/308 ,  H01L21/8242

CPC分类号： H01L21/3081 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.

摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。

公开(公告)号：US20050151213A1

公开(公告)日：2005-07-14

申请号：US10707746

申请日：2004-01-08

申请人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Jon Casey ,  William Ferrante ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L21/00 ,  H01L27/14 ,  H01L29/82 ,  H01L31/058

CPC分类号： H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

摘要： A structure and method are provided for forming a thermistor. Isolation structures are formed in a substrate including at least an upper layer of a single crystal semiconductor. A layer of salicide precursor is deposited over the isolation region and the upper layer. The salicide precursor is then reacted with the upper layer to form a salicide self-aligned to the upper layer. Finally, the unreacted portions of the salicide precursor are then removed while preserving a portion of the salicide precursor over the isolation region as a body of the thermistor. An alternative integrated circuit thermistor is formed from a region of thermistor material in an embossed region of an interlevel dielectric (ILD).

摘要翻译： 提供了用于形成热敏电阻的结构和方法。 隔离结构形成在至少包括单晶半导体的上层的基板中。 一层自杀化合物前体沉积在隔离区和上层上。 然后将自对准硅化物前体与上层反应以形成与上层自对准的自对准硅化物。 最后，除去自对准硅胶前体的未反应部分，同时在作为热敏电阻体的隔离区域上保留一部分自杀化合物前体。 一种替代的集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料的区域形成。

公开(公告)号：US06548358B2

公开(公告)日：2003-04-15

申请号：US09769494

申请日：2001-01-26

申请人： Kenneth C. Arndt ,  Dureseti Chidambarrao ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl Radens

发明人： Kenneth C. Arndt ,  Dureseti Chidambarrao ,  Louis L. Hsu ,  Jack A. Mandelman ,  Carl Radens

IPC分类号： H01L21336

CPC分类号： H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

摘要翻译： 半导体保险丝位于用于连接布线的导体之间。 保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。 导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。

公开(公告)号：US06258689B1

公开(公告)日：2001-07-10

申请号：US09626328

申请日：2000-07-26

申请人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

发明人： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

IPC分类号： H01L2120

CPC分类号： H01L27/10861 ,  H01L29/66181

摘要： Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

摘要翻译： 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。

公开(公告)号：US6013937A

公开(公告)日：2000-01-11

申请号：US938196

申请日：1997-09-26

申请人： Jochen Beintner ,  Ulrike Gruening ,  Carl Radens

发明人： Jochen Beintner ,  Ulrike Gruening ,  Carl Radens

IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/00 ,  H01L21/336 ,  H01L21/469 ,  H01L29/06

CPC分类号： H01L27/1087 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/763 ,  H01L27/10867 ,  Y10S438/97

摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

摘要翻译： 设置在半导体衬底102上的衬垫层和布置在焊盘层内的缓冲层108，使得衬垫层被分为缓冲层下面的介电层106和缓冲层上方的掩模层110。 在半导体芯片上形成具有均匀平坦度和厚度的层的方法包括以下步骤：提供具有形成在其上的热垫106的衬底，在热衬垫上形成电介质层106，在电介质层上形成缓冲层108，其中， 缓冲层由与电介质层不同的材料制成，并在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。

公开(公告)号：US08207028B2

公开(公告)日：2012-06-26

申请号：US12017598

申请日：2008-01-22

申请人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

发明人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl Radens

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

摘要翻译： 具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的第一纳米级自对准自组装嵌套线结构由第一层内的第一自组装嵌段共聚物形成。 第一层填充有填充材料，并且第二层沉积在包含第一纳米级嵌套线结构的第一层之上。 具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层内的第二自组装嵌段共聚物形成。 第一纳米级嵌套线结构和第二纳米级嵌套线结构的复合图案被转移到第一层下面的底层中以形成在两个方向上包含周期性的结构阵列。

公开(公告)号：US20080261369A1

公开(公告)日：2008-10-23

申请号：US12121922

申请日：2008-05-16

申请人： Dureseti Chidambarrao ,  Carl Radens

发明人： Dureseti Chidambarrao ,  Carl Radens

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

摘要翻译： 本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。 本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。 本发明还提供了利用该方法形成的半导体结构。 半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

公开(公告)号：US20080179680A1

公开(公告)日：2008-07-31

申请号：US12054812

申请日：2008-03-25

申请人： Dureseti CHIDAMBARRAO ,  Anda C. Mocuta ,  Dan M. Mocuta ,  Carl Radens

发明人： Dureseti CHIDAMBARRAO ,  Anda C. Mocuta ,  Dan M. Mocuta ,  Carl Radens

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

摘要翻译： 本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。 在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。 此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。