公开(公告)号：USD954602S1

公开(公告)日：2022-06-14

申请号：US29764840

申请日：2021-01-04

申请人： Nicholas A. Malachowski ,  Eugenio Sellaro-Neto ,  Matthew W. Dunford ,  Alexander Tannen ,  Chris Piscitelli ,  Jeffrey C. Gale ,  Mark D. Hall ,  Mark T. Allen

设计人： Nicholas A. Malachowski ,  Eugenio Sellaro-Neto ,  Matthew W. Dunford ,  Alexander Tannen ,  Chris Piscitelli ,  Jeffrey C. Gale ,  Mark D. Hall ,  Mark T. Allen

公开(公告)号：US20170337049A1

公开(公告)日：2017-11-23

申请号：US15156663

申请日：2016-05-17

申请人： David R. Hall ,  Mark D. Hall ,  Craig Boswell ,  Jedediah Knight

发明人： David R. Hall ,  Mark D. Hall ,  Craig Boswell ,  Jedediah Knight

IPC分类号： G06F9/445 ,  H04W4/00 ,  H04L27/12 ,  H04W24/04 ,  H04B1/69

CPC分类号： H04W24/04 ,  H04L12/2834 ,  H04L43/0817 ,  H04L43/10 ,  H04W4/50

摘要： A redundant star network is disclosed. The network includes a peripheral device (PD), a control hub, and a backup hub. The control hub and backup hub each have a wireless long range transceiver, hardware processors, and hardware memory. The PD includes a wireless long range transceiver and a microcontroller. The control hub and backup hub hardware memories store system operation information. The system operation information includes instructions for controlling the PD. The PD microcontroller includes test firmware and update firmware. The test firmware instructs the PD to test the control hub and to listen for a test response signal indicating the control hub is operational. The PD update firmware instructs the PD to switch control of the PD to the backup hub when the test response signal is not received within an expected response timeframe after the test signal is sent.

公开(公告)号：US08951892B2

公开(公告)日：2015-02-10

申请号：US13539070

申请日：2012-06-29

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/02 ,  H01L29/66 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B60C23/00 ,  B81B1/00 ,  B81B2203/0361 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01L9/06 ,  G01N33/0031 ,  G02B6/107 ,  G02B6/126 ,  G02B2006/12097 ,  H01L21/3086 ,  H01L29/0665 ,  H01L29/66 ,  H01L33/18 ,  H01L41/1132 ,  H01L43/02

摘要： A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

摘要翻译： 公开的制造混合纳米柱装置的方法包括在基底上形成掩模和硬掩模上的纳米团簇层。 然后蚀刻硬掩模以将由第一层纳米团簇形成的图案转移到硬掩模的第一区域中。 在基板上形成第二纳米团簇层。 蚀刻覆盖衬底的第二区域的硬掩模的第二区域，以在硬掩模中产生第二图案。 然后将衬底通过硬掩模蚀刻以在衬底的第一区域中形成第一组纳米柱，并在衬底的第二区域中形成第二组纳米柱。 通过改变第一和第二层纳米团簇之间的纳米团簇沉积步骤，第一组和第二组纳米颗粒将呈现不同的特征。

公开(公告)号：US08906764B2

公开(公告)日：2014-12-09

申请号：US13441426

申请日：2012-04-06

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在NVM工作功能设定金属上，NVM工作功能设定金属位于高k电介质上，逻辑晶体管的金属逻辑门类似地形成工作功能设定和高电平 -k电介质材料。 在形成NVM单元的金属选择栅极的部分的同时形成逻辑晶体管。 在形成NVM单元的同时，保护逻辑晶体管，包括使用纳米晶体形成电荷存储区域，并在金属选择栅极的一部分上形成金属控制栅极以及在基板上的电荷存储区域的一部分。 蚀刻电荷存储区域以与金属控制栅极对准。

公开(公告)号：US08564044B2

公开(公告)日：2013-10-22

申请号：US13077491

申请日：2011-03-31

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L29/788 ,  H01L21/70 ,  H01L21/4763

CPC分类号： H01L29/42344 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/42332

摘要： An integrated circuit is disclosed that includes a split gate memory device comprising a select gate is located over a substrate. A charge storage layer includes a layer of discrete storage elements and a layer of high-k dielectric material covering at least one side of the layer of discrete storage elements. At least a portion of a control gate is located over the charge storage layer. The control gate includes a layer of barrier work function material and a layer of gate material located over the layer of barrier work function material.

摘要翻译： 公开了一种集成电路，其包括分离栅极存储器件，其包括位于衬底上方的选择栅极。 电荷存储层包括分立的存储元件层和覆盖分立存储元件层的至少一侧的高k电介质材料层。 控制栅极的至少一部分位于电荷存储层上方。 控制门包括一层屏障功能材料和位于屏障功能材料层之上的一层栅极材料。

公开(公告)号：US08536007B2

公开(公告)日：2013-09-17

申请号：US13402426

申请日：2012-02-22

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/8246

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42348

摘要： A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.

摘要翻译： 图案化第一导电层和底层电荷存储层，以在NVM区域中形成控制栅极。 第一介电层形成在控制栅上。 牺牲层形成在第一电介质层上并且被平坦化。 在牺牲层上形成图案化掩模层，该牺牲层包括限定在NVM区域中与控制栅极横向相邻的选择栅极位置的第一部分和在逻辑区域中限定逻辑门的第二部分。 去除牺牲层的暴露部分，使得第一部分保持在选择栅极位置。 在第一部分上形成第二电介质层并将其平坦化以暴露第一部分。 第一部分被去除以导致选择门位置处的打开。 在开口中形成栅介质层和选择栅极。

公开(公告)号：US20130137227A1

公开(公告)日：2013-05-30

申请号：US13307719

申请日：2011-11-30

申请人： MEHUL D. SHROFF ,  Mark D. Hall

发明人： MEHUL D. SHROFF ,  Mark D. Hall

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

摘要翻译： 一种方法包括在NVM区域和逻辑区域中的衬底上形成栅极电介质; 在NVM区域和逻辑区域中的栅极电介质上形成第一导电层; 图案化NVM区域中的第一导电层以形成选择栅极; 在NVM区域的选择栅极和逻辑区域中的第一导电层上形成电荷存储层; 在NVM区域和逻辑区域中的电荷存储层上形成第二导电层; 从所述逻辑区域去除所述第二导电层和所述电荷存储层; 图案化逻辑区域中的第一导电层以形成第一逻辑门; 并且在形成第一逻辑门之后，对NVM区域中的第二导电层进行构图以形成与选择栅极的侧壁重叠的控制栅极。

公开(公告)号：US20120068305A1

公开(公告)日：2012-03-22

申请号：US12886859

申请日：2010-09-21

申请人： MEHUL D. SHROFF ,  Mark D. Hall

发明人： MEHUL D. SHROFF ,  Mark D. Hall

IPC分类号： H01L27/08 ,  H01L21/02

CPC分类号： H01L28/87 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.

摘要翻译： 在半导体衬底上形成有源器件区域。 互连层形成在有源器件区域上，其中互连层包括具有第一介电常数的第一介电材料，第一电介质材料中的第一金属互连和第一介电材料中的第二金属互连，并且横向间隔开 从第一个金属互连。 去除第一介电材料的一部分，使得第一电介质材料的剩余部分保留在互连层内，其中去除部分从第一和第二金属互连之间的位置移除。 第一和第二金属互连之间的第一介电材料部分被去除的位置用第二介电常数填充，第二介电常数高于第一介电常数。

公开(公告)号：US20110291180A1

公开(公告)日：2011-12-01

申请号：US12787101

申请日：2010-05-25

申请人： Mark D. Hall

发明人： Mark D. Hall

IPC分类号： H01L27/115 ,  H01L29/772 ,  H01L21/8239

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.

摘要翻译： 角度离子注入用于在形成在掩模开口中的半导体柱中形成掺杂区域。 支柱形成为小于面罩高度的高度。 角度离子注入可用于形成半导体器件的区域，例如半导体器件实体的半导体器件的主体连接区域，晕圈区域或电流端子延伸区域。

公开(公告)号：US20090274137A1

公开(公告)日：2009-11-05

申请号：US12114312

申请日：2008-05-02

申请人： Mark D. Hall ,  Timothy M. Force

发明人： Mark D. Hall ,  Timothy M. Force

IPC分类号： H04J3/00

CPC分类号： H04W56/001 ,  H04J3/0644

摘要： A mobile ad hoc network, a mobile ad hoc network node and a method for establishing a system time within a mobile ad hoc network are provided. The network nodes may include a global positioning system (GPS) receiver for receiving GPS signals and for providing a GPS time derived from the GPS signals. The GPS time may be employed by the network node as the system time. Even though the network nodes of a mobile ad hoc network independently determine the GPS time and, in turn, the system time, the system time will be common for each of the network nodes. Mobile ad hoc network nodes may therefore join and leave the mobile ad hoc network with each network node being able to determine the system time prior to its joinder based upon the GPS time provided by the respective GPS receiver.

摘要翻译： 提供了移动自组织网络，移动自组织网络节点和用于在移动自组织网络内建立系统时间的方法。 网络节点可以包括用于接收GPS信号并提供从GPS信号导出的GPS时间的全球定位系统（GPS）接收机。 GPS时间可以由网络节点用作系统时间。 即使移动自组织网络的网络节点独立地确定GPS时间，并且依次确定系统时间，系统时间对于每个网络节点将是共同的。 因此，移动自组织网络节点可以加入并离开移动自组织网络，每个网络节点能够根据由相应的GPS接收机提供的GPS时间来确定其加入之前的系统时间。