公开(公告)号：US20130130406A1

公开(公告)日：2013-05-23

申请号：US13720074

申请日：2012-12-19

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Seung H. Kang ,  Xia Li

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G01R33/098 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3259 ,  H01F10/3268 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L27/228 ,  H01L43/08

Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer.

Abstract translation: 公开了一种磁隧道结（MTJ）装置及其制造方法。 在特定实施例中，公开了一种包括MTJ装置的装置。 MTJ装置包括自由层和自旋转矩增强层。 自旋扭矩增强层包括纳米氧化物层。

公开(公告)号：US20130119497A1

公开(公告)日：2013-05-16

申请号：US13734685

申请日：2013-01-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L29/66 ,  H01L21/67 ,  H01L29/82

CPC classification number: H01L21/67011 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/53165

Abstract: A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure.

Abstract translation: 通过包括在衬底中形成沟槽并在沟槽内沉积MTJ结构的工艺形成磁隧道结（MTJ）器件。 MTJ结构包括底电极，固定层，隧道势垒层，自由层和顶电极。 该方法包括施加反向光刻蚀以除去不直接在沟槽上的材料。 该方法还包括抄袭MTJ结构，而不对MTJ结构执行光蚀刻工艺。

公开(公告)号：US20130062716A1

公开(公告)日：2013-03-14

申请号：US13663806

申请日：2012-10-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L29/82 ,  H01L21/02

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  G11C2211/5615 ,  H01F10/3254 ,  H01F41/308 ,  H01L27/222 ,  H01L43/08

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract translation: 公开了一种形成磁性隧道结装置的方法，其包括在衬底中形成沟槽，沟槽包括多个侧壁和底壁。 所述方法包括在所述沟槽内靠近所述侧壁之一沉积第一导电材料，并在所述沟槽内沉积第二导电材料。 该方法还包括沉积材料以在沟槽内形成磁隧道结（MTJ）结构。 MTJ结构包括具有固定磁性取向的磁场的固定磁性层，隧道结层和具有可配置磁性取向的磁场的自由磁性层。 该方法还包括选择性地移除MTJ结构的一部分以在MTJ结构中形成开口。

公开(公告)号：US12224347B2

公开(公告)日：2025-02-11

申请号：US17180219

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Haining Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：US20240421157A1

公开(公告)日：2024-12-19

申请号：US18336269

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming-Huei Lin ,  Haining Yang

IPC: H01L27/092 ,  H01L21/8238

Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region to improve carrier mobility, thereby increasing drive strength. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region to further improve carrier mobility. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

公开(公告)号：US20240379679A1

公开(公告)日：2024-11-14

申请号：US18314245

申请日：2023-05-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Jun Yuan

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

Abstract: A 3D dual complementary-circuit structure includes a first forksheet structure stacked on a first side of, in a first direction, a second forksheet structure to provide two complementary circuits in a space of a single forksheet structure. A dividing wall bisects at least one semiconductor slab in the first forksheet structure into a first slab portion with a first semiconductor type and a second slab portion with a second semiconductor type and also bisects at least one semiconductor slab in the second forksheet structure into a third slab portion with a third semiconductor type and a fourth slab portion with a fourth semiconductor type. One of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type may be a same semiconductor type as the first semiconductor type. Two complementary metal oxide semiconductor (CMOS) circuits may be formed in the area of a single forksheet structure.

公开(公告)号：US12108610B2

公开(公告)日：2024-10-01

申请号：US17313834

申请日：2021-05-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/20 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

公开(公告)号：US11710789B2

公开(公告)日：2023-07-25

申请号：US17369532

申请日：2021-07-07

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Junjing Bao

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L27/092 ,  H01L29/24 ,  H01L29/517 ,  H01L29/66969

Abstract: Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

公开(公告)号：US20230061693A1

公开(公告)日：2023-03-02

申请号：US17410690

申请日：2021-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Bin Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Three-dimensional (3D) interconnect structures employing via layer conductive structures in via layers are disclosed. The via layer conductive structures in a signal path in an interconnect structure are disposed in respective via layers adjacent to metal lines in metal layers. The via layer conductive structures increase the conductive cross-sections of signal paths between devices in an integrated circuit (IC) or to/from an external contact. The via layer conductive structures provide one or both of supplementing the height dimensions of metal lines and electrically coupling metal lines in the same or different metal layers to increase the conductive cross-section of a signal path. The increased conductive cross-section reduces current-resistance (IR) drop of signals and increases signal speed. As metal track pitches are reduced in size, signal path resistance increases. The via layer conductive structures are provided to reduce or avoid an even greater increase in resistance in the signal paths.

公开(公告)号：US11474786B2

公开(公告)日：2022-10-18

申请号：US16778749

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Zhongze Wang ,  Periannan Chidambaram

IPC: G06F7/533 ,  G06F7/53 ,  G06F7/523

Abstract: Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.