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    Fractional-readout oversampled image sensor
    101.
    发明授权
    Fractional-readout oversampled image sensor 有权

    公开(公告)号：US10362256B2

    公开(公告)日：2019-07-23

    申请号：US15759963

    申请日：2016-09-20

    Applicant: Rambus Inc.

    Inventor： Jay Endsley ,  Thomas Vogelsang ,  Craig M. Smith ,  Michael Guidash ,  Alexander C. Schneider

    IPC: H04N5/235 ,  H04N5/353 ,  H04N5/355 ,  H04N5/378

    Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.

    Shared-counter image sensor
    102.
    发明授权
    Shared-counter image sensor 有权

    公开(公告)号：US10264195B1

    公开(公告)日：2019-04-16

    申请号：US15805024

    申请日：2017-11-06

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang

    IPC: H04N5/353 ,  H04N5/355 ,  H04N5/378 ,  H04N5/3745

    Abstract: An image sensor generates first digital samples and second digital samples during respective first and second sampling intervals, the first digital samples including at least one digital sample of each pixel of a first plurality of pixels, and the second digital samples including at least one digital sample of each pixel of a second plurality of pixels. A sum of the first digital samples is accumulated within a first counter as the first sampling interval transpires, and a sum of the second digital samples is accumulated within the first counter as the second sampling interval transpires.

    REDUCED TRANSPORT ENERGY IN A MEMORY SYSTEM
    103.
    发明申请
    REDUCED TRANSPORT ENERGY IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20180197596A1

    公开(公告)日：2018-07-12

    申请号：US15876539

    申请日：2018-01-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

    IPC: G11C11/4093 ,  G11C11/4094 ,  G11C11/4076

    CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

    Multi-die DRAM banks arrangement and wiring
    107.
    发明授权
    Multi-die DRAM banks arrangement and wiring 有权
    多芯片DRAM库布局和布线

    公开(公告)号：US09548102B2

    公开(公告)日：2017-01-17

    申请号：US14807786

    申请日：2015-07-23

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang

    IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/408 ,  G11C5/06 ,  G11C8/12

    CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C8/12 ,  G11C11/4082

    Abstract: The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory die with a plurality of memory banks and a plurality of contacts. The method includes: (1) coupling a first memory bank of the plurality of memory banks to a second memory die via the plurality of contacts; (2) transmitting data between the first memory bank and the second memory die via the plurality of contacts; and (3) receiving a control signal to couple a second memory bank of the plurality of memory banks to the second memory die. The method further includes, in response to receiving the control signal, coupling the second memory bank to the second memory die via the plurality of contacts; and transmitting data between the second memory bank and the second memory die via the plurality of contacts.

    Abstract translation: 这里描述的各种实施例包括存储器管芯和用于存储器管芯通信的方法。 一方面，在具有多个存储体和多个触点的第一存储模具处执行一种方法。 该方法包括：（1）通过多个触点将多个存储体的第一存储体耦合到第二存储管芯; （2）经由多个触点在第一存储体和第二存储管芯之间传输数据; 和（3）接收控制信号以将所述多个存储器组的第二存储体耦合到所述第二存储器管芯。 该方法还包括响应于接收到控制信号，经由多个触点将第二存储体耦合到第二存储器管芯; 以及经由所述多个触点在所述第二存储体和所述第二存储管芯之间传输数据。

    LOW-NOISE, HIGH DYNAMIC-RANGE IMAGE SENSOR
    109.
    发明申请
    LOW-NOISE, HIGH DYNAMIC-RANGE IMAGE SENSOR 有权
    低噪声，高动态范围图像传感器

    公开(公告)号：US20160028974A1

    公开(公告)日：2016-01-28

    申请号：US14807794

    申请日：2015-07-23

    Applicant: Rambus Inc.

    Inventor： Michael Guidash ,  Thomas Vogelsang ,  Jay Endsley ,  James E. Harris ,  Craig M. Smith ,  John Ladd ,  Michael T. Ching

    IPC: H04N5/357 ,  H04N5/355 ,  H04N5/378

    CPC classification number: H04N5/3655 ,  H04N5/355 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/3651 ,  H04N5/3698 ,  H04N5/3745 ,  H04N5/37455 ,  H04N5/378

    Abstract: An integrated-circuit image sensor generates, as constituent reference voltages of a first voltage ramp, a first sequence of linearly related reference voltages followed by a second sequence of exponentially related reference voltages. The integrated-circuit image sensor compares the constituent reference voltages of the first voltage ramp with a first signal level representative of photocharge integrated within a pixel of the image sensor to identify a first reference voltage of the constituent reference voltages that is exceeded by the first signal level

    Abstract translation: 作为第一电压斜坡的组成参考电压的集成电路图像传感器产生第二线性相关参考电压序列，随后是第二指数相关参考电压序列。 集成电路图像传感器将第一电压斜坡的构成参考电压与表示在图像传感器的像素内集成的光电荷的第一信号电平进行比较，以识别由第一信号超过的构成参考电压的第一参考电压 水平

    Multi-Die DRAM Banks Arrangement and Wiring
    110.
    发明申请
    Multi-Die DRAM Banks Arrangement and Wiring 有权
    多模DRAM银行的布置和布线

    公开(公告)号：US20150348613A1

    公开(公告)日：2015-12-03

    申请号：US14807786

    申请日：2015-07-23

    Applicant: Rambus Inc.

    Inventor： Thomas Vogelsang

    IPC: G11C11/4093 ,  G11C11/408

    CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C8/12 ,  G11C11/4082

    Abstract: The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory die with a plurality of memory banks and a plurality of contacts. The method includes: (1) coupling a first memory bank of the plurality of memory banks to a second memory die via the plurality of contacts; (2) transmitting data between the first memory bank and the second memory die via the plurality of contacts; and (3) receiving a control signal to couple a second memory bank of the plurality of memory banks to the second memory die. The method further includes, in response to receiving the control signal, coupling the second memory bank to the second memory die via the plurality of contacts; and transmitting data between the second memory bank and the second memory die via the plurality of contacts.

    Abstract translation: 这里描述的各种实施例包括存储器管芯和用于存储器管芯通信的方法。 一方面，在具有多个存储体和多个触点的第一存储模具处执行一种方法。 该方法包括：（1）通过多个触点将多个存储体的第一存储体耦合到第二存储管芯; （2）经由多个触点在第一存储体和第二存储管芯之间传输数据; 和（3）接收控制信号以将所述多个存储器组的第二存储体耦合到所述第二存储器管芯。 该方法还包括响应于接收到控制信号，经由多个触点将第二存储体耦合到第二存储器管芯; 以及经由所述多个触点在所述第二存储体和所述第二存储管芯之间传输数据。

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