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公开(公告)号:US10861984B2
公开(公告)日:2020-12-08
申请号:US16564860
申请日:2019-09-09
Applicant: STMicroelectronics, Inc.
Inventor: Qing Liu , John H. Zhang
Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.
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公开(公告)号:US10749031B2
公开(公告)日:2020-08-18
申请号:US15273778
申请日:2016-09-23
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, Inc. , STMICROELECTRONICS, INC.
Inventor: Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC: H01L29/78 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/45 , H01L21/02 , H01L21/8234 , H01L21/768 , H01L21/285
Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
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103.
公开(公告)号:US10580771B2
公开(公告)日:2020-03-03
申请号:US16049685
申请日:2018-07-30
Applicant: STMICROELECTRONICS, INC.
Inventor: Qing Liu , Prasanna Khare , Nicolas Loubet
IPC: H01L21/84 , H01L29/66 , H01L29/78 , H01L21/8238 , H01L27/088 , H01L29/08 , H01L21/265 , H01L29/417 , H01L21/225 , H01L21/8234
Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.
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104.
公开(公告)号:US10355020B2
公开(公告)日:2019-07-16
申请号:US15180860
申请日:2016-06-13
Applicant: International Business Machines Corporation , GLOBALFOUNDRIES INC. , STMICROELECTRONICS, INC.
Inventor: Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh
IPC: H01L27/12 , H01L29/417 , H01L29/66 , H01L21/8234 , H01L21/28 , H01L29/06 , H01L29/10 , H01L29/78 , G06N3/04 , G10L15/16 , H01L29/36
Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
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公开(公告)号:US10324254B2
公开(公告)日:2019-06-18
申请号:US15962633
申请日:2018-04-25
Applicant: STMicroelectronics, Inc.
Inventor: Qing Liu
IPC: G02B6/10 , G02B6/136 , G02B6/122 , C30B23/04 , C30B25/04 , C30B29/06 , G02B6/13 , G02B6/12 , G02B6/032
Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.
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公开(公告)号:US10243074B2
公开(公告)日:2019-03-26
申请号:US15693938
申请日:2017-09-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, INC. , STMicroelectronics, Inc.
Inventor: Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC: H01L21/02 , H01L29/66 , H01L29/78 , H01L21/306 , H01L21/324 , H01L29/417
Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
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公开(公告)号:US10084080B2
公开(公告)日:2018-09-25
申请号:US14675298
申请日:2015-03-31
Applicant: STMICROELECTRONICS, INC.
Inventor: Qing Liu , John H. Zhang
IPC: H01L29/66 , H01L21/8238 , H01L21/336 , H01L29/78 , H01L29/165 , H01L29/267 , H01L29/739 , H01L27/092 , H01L29/16 , H01L21/8234 , H01L29/49 , H01L29/51
CPC classification number: H01L29/7827 , H01L21/823487 , H01L21/823885 , H01L27/092 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/4958 , H01L29/517 , H01L29/66356 , H01L29/66666 , H01L29/7391 , H01L29/785
Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.
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公开(公告)号:US20180102432A1
公开(公告)日:2018-04-12
申请号:US15693938
申请日:2017-09-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, INC. , STMicroelectronics, Inc.
Inventor: Qing Liu , Ruilong Xie , Chun-chen Yeh
IPC: H01L29/78 , H01L29/66 , H01L29/417 , H01L21/324 , H01L21/02 , H01L21/306
CPC classification number: H01L29/7827 , H01L21/02614 , H01L21/30604 , H01L21/324 , H01L29/41741 , H01L29/66553 , H01L29/66666
Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
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公开(公告)号:US09922883B2
公开(公告)日:2018-03-20
申请号:US15180158
申请日:2016-06-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES INC. , STMICROELECTRONICS, INC.
Inventor: Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC: H01L27/12 , H01L21/8238 , H01L29/08 , H01L29/786 , H01L21/84 , H01L21/768 , H01L29/78
CPC classification number: H01L21/823807 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/7842 , H01L29/7848 , H01L29/786 , H01L29/78684
Abstract: A method for making a semiconductor device is provided. Raised source and drain regions are formed with a tensile strain-inducing material, after thermal treatment to form source drain extension regions, to thereby preserve the strain-inducing material in desired substitutional states.
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公开(公告)号:US20180076306A1
公开(公告)日:2018-03-15
申请号:US15806160
申请日:2017-11-07
Applicant: STMICROELECTRONICS, INC.
Inventor: Qing Liu
CPC classification number: H01L29/66818 , H01L29/6653 , H01L29/66545 , H01L29/66795 , H01L29/7834 , H01L29/7843 , H01L29/785
Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.
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