公开(公告)号：US10741265B2

公开(公告)日：2020-08-11

申请号：US15924100

申请日：2018-03-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20200242461A1

公开(公告)日：2020-07-30

申请号：US16360955

申请日：2019-03-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/4063 ,  G06F12/0811

Abstract: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.

公开(公告)号：US20200051636A1

公开(公告)日：2020-02-13

申请号：US16550253

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20190205729A1

公开(公告)日：2019-07-04

申请号：US15936983

申请日：2018-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/04 ,  G11C16/04 ,  G06F17/16 ,  G06N3/063

CPC classification number: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C16/0425 ,  H03F3/45269

Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

公开(公告)号：US20190115088A1

公开(公告)日：2019-04-18

申请号：US16218398

申请日：2018-12-12

Applicant: Silicon STorage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/16 ,  G11C5/14 ,  G11C16/10 ,  G11C8/08

Abstract: During a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

公开(公告)号：US10236068B2

公开(公告)日：2019-03-19

申请号：US15873872

申请日：2018-01-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28 ,  G11C16/14 ,  G11C16/24 ,  G11C7/06 ,  G11C16/04

Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.

公开(公告)号：US10199112B1

公开(公告)日：2019-02-05

申请号：US15687092

申请日：2017-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/34

Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.

公开(公告)号：US20170337978A1

公开(公告)日：2017-11-23

申请号：US15158460

申请日：2016-05-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

CPC classification number: G11C16/3431 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US09747986B2

公开(公告)日：2017-08-29

申请号：US15003811

申请日：2016-01-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC: G06F17/50 ,  G11C16/08 ,  G11C11/16 ,  G11C13/00 ,  G11C16/28

CPC classification number: G11C16/08 ,  G06F17/5081 ,  G11C7/062 ,  G11C8/10 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26 ,  G11C16/28

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

公开(公告)号：US09620216B2

公开(公告)日：2017-04-11

申请号：US14624476

申请日：2015-02-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/08 ,  G11C17/08 ,  G11C16/22 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/14 ,  G11C16/22 ,  G11C16/26 ,  G11C17/08 ,  G11C2216/26

Abstract: The disclosed embodiments comprise a flash memory device that can be configured to operate as a read only memory device. In some embodiments, the flash memory device can be configured into a flash memory portion and a read only memory portion.