公开(公告)号：US20190112183A1

公开(公告)日：2019-04-18

申请号：US16211681

申请日：2018-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng

IPC: B81C1/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a plurality of interconnect layers disposed within a dielectric structure over a substrate. A passivation layer is over the dielectric structure. A sensing electrode and a bonding electrode have bottom surfaces directly contacting the passivation layer. A microelectromechanical systems (MEMS) substrate is vertically separated from the sensing electrode. The bonding electrode is electrically connected to the MEMs substrate and to one or more of the plurality of interconnect layers. An electrode extension via is configured to electrically connect the sensing electrode to one or more of the plurality of interconnect layers.

公开(公告)号：US20190055120A1

公开(公告)日：2019-02-21

申请号：US16167912

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Chia-Hua Chu

IPC: B81C1/00 ,  H01L23/532 ,  H01L21/82

CPC classification number: B81C1/00246 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L21/82 ,  H01L23/53295 ,  H01L2924/1461

Abstract: An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.

公开(公告)号：US10138116B2

公开(公告)日：2018-11-27

申请号：US15716676

申请日：2017-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Chia-Hua Chu

IPC: H01L23/532 ,  B81C1/00 ,  H01L21/82

Abstract: An integrated circuit (IC) with an integrated microelectromechanical systems (MEMS) structure is provided. In some embodiments, the IC comprises a semiconductor substrate, a back-end-of-line (BEOL) interconnect structure, the integrated MEMS structure, and a cavity. The BEOL interconnect structure is over the semiconductor substrate, and comprises wiring layers stacked in a dielectric region. Further, an upper surface of the BEOL interconnect structure is planar or substantially planar. The integrated MEMS structure overlies and directly contacts the upper surface of the BEOL interconnect structure, and comprises an electrode layer. The cavity is under the upper surface of the BEOL interconnect structure, between the MEMS structure and the BEOL interconnect structure.

公开(公告)号：US09910009B2

公开(公告)日：2018-03-06

申请号：US15661798

申请日：2017-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

IPC: H01L51/05 ,  G01N27/414 ,  H01L27/12 ,  H01L21/84 ,  H01L51/00

CPC classification number: G01N27/4145 ,  G01N27/414 ,  G01N27/4148 ,  H01L21/84 ,  H01L27/1203 ,  H01L51/0093

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

公开(公告)号：US20170369308A1

公开(公告)日：2017-12-28

申请号：US15193410

申请日：2016-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng

IPC: B81C1/00

CPC classification number: B81C1/00238 ,  B81C2203/0785

Abstract: The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes dielectric layers and etch stop layers that are stacked in an alternating fashion. Metal wire layers are disposed within the stacked structure of the IMD region. The structure also includes a sensing electrode electrically connected to the IMD region with an electrode extension via. The structure includes a MEMS substrate comprising a MEMS device having a soft mechanical structure positioned adjacent to the sensing electrode.

公开(公告)号：US09617150B2

公开(公告)日：2017-04-11

申请号：US14049988

申请日：2013-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: B81C3/00 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/0035 ,  B81B7/0041 ,  B81C1/00793 ,  B81C2201/013 ,  B81C2201/053 ,  B81C2203/0118 ,  B81C2203/0792

Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate and a MEMS substrate bonded with the CMOS substrate. The CMOS substrate includes a semiconductor substrate, a first dielectric layer formed over the semiconductor substrate, and a plurality of conductive pads formed in the first dielectric layer. The MEMS substrate includes a semiconductor layer having a movable element and a second dielectric layer formed between the semiconductor layer and the CMOS substrate. The MEMS substrate also includes a closed chamber surrounding the movable element. The MEMS substrate further includes a blocking layer formed between the closed chamber and the first dielectric layer of the CMOS substrate. The blocking layer is configured to block gas, coming from the first dielectric layer, from entering the closed chamber.

公开(公告)号：US20170057814A1

公开(公告)日：2017-03-02

申请号：US15170154

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Chia-Hua Chu ,  Jung-Huei Peng

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B3/001 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2201/0132 ,  B81C2203/035 ,  B81C2203/037 ,  B81C2203/0792 ,  H01L2224/16

Abstract: The present disclosure relates an integrated chip having one or more MEMS devices. In some embodiments, the integrated chip has a carrier substrate with one or more cavities disposed within a first side of the carrier substrate. A dielectric layer is disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate. The dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities. A bonding structure, including an intermetallic compound having a plurality of metallic elements, abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate.

Abstract translation: 本公开涉及具有一个或多个MEMS器件的集成芯片。 在一些实施例中，集成芯片具有载体衬底，其具有设置在载体衬底的第一侧内的一个或多个空腔。 电介质层设置在载体衬底的第一侧和微机电系统（MEMS）衬底的第一侧之间。 电介质层具有侧壁，该侧壁从延伸穿过MEM衬底的开口的侧壁横向设置到一个或多个空腔。 包括具有多个金属元素的金属间化合物的接合结构邻接在MEMS基板的第二面上，并且电连接到设置在CMOS基板上的电介质结构内的金属互连层。

公开(公告)号：US20170016851A1

公开(公告)日：2017-01-19

申请号：US15277108

申请日：2016-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Fei-Lung Lai ,  Chia-Hua Chu ,  Yi-Hsien Chang ,  Hsin-Chieh Huang

IPC: G01N27/414 ,  H01L23/522 ,  H01L23/528 ,  H01L21/48

CPC classification number: G01N27/4148 ,  G01N27/4145 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a substrate, and a lower metal wire over the substrate and electrically coupled to the sensing device. First and second metal vias are arranged on the lower metal wire at locations set back from sidewalls of the lower metal wire, and first and second upper metal wires respectively cover top surfaces of the first and second metal vias. A dielectric structure surrounds the lower metal wire, the first and second metal vias, and the first and second upper metal wires. A sensing well has sensing surfaces that extend along an upper surface of the lower metal wire and along sidewalls of the first and second metal vias and the first and second upper metal wires.

Abstract translation: 本公开涉及具有具有水平和垂直感测表面的集成生物传感器的集成芯片。 在一些实施例中，集成芯片具有设置在衬底内的感测装置，以及位于衬底上的电子耦合到感测装置的下部金属线。 第一和第二金属通孔设置在下金属线上，从下金属线的侧壁设置的位置，第一和第二上金属线分别覆盖第一和第二金属通孔的顶表面。 电介质结构围绕下金属线，第一和第二金属通孔以及第一和第二上金属线。 感测井具有沿着下金属线的上表面并且沿着第一和第二金属通孔以及第一和第二上金属线的侧壁延伸的感测表面。

公开(公告)号：US09522822B2

公开(公告)日：2016-12-20

申请号：US14276445

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Cheng ,  Chia-Hua Chu

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/02 ,  H01L23/00 ,  H01L25/16

CPC classification number: B81C1/0023 ,  B81B7/0041 ,  B81B7/0077 ,  B81B2207/012 ,  B81C1/00269 ,  H01L23/02 ,  H01L24/02 ,  H01L25/16

Abstract: The present disclosure relates to a structure and method of forming a MEMS-CMOS integrated circuit with an outgassing barrier and a stable electrical signal path. An additional poly or metal layer is embedded within the MEMS die to prevent outgassing from the CMOS die. Patterned conductors formed by a damascene process and a direct bonding between the two dies provide a stable electrical signal path.

Abstract translation: 本公开涉及一种具有放气屏障和稳定的电信号路径的MEMS-CMOS集成电路的结构和方法。 另外的多晶硅或金属层被嵌入在MEMS管芯内，以防止从CMOS管芯脱气。 通过镶嵌工艺形成的图形导体和两个管芯之间的直接接合提供了稳定的电信号路径。

公开(公告)号：US09462402B2

公开(公告)日：2016-10-04

申请号：US14620368

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yi Cho ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng ,  Yao-Te Huang

IPC: H01R31/00 ,  H04R31/00 ,  H04R19/04

CPC classification number: H04R1/04 ,  H04R19/005 ,  H04R19/04

Abstract: Some embodiments relate to a manufacturing process that combines a MEMS capacitor of a microelectromechanical systems (MEMS) microphone and an integrated circuit (IC) onto a single substrate. A dielectric is formed over a device substrate. A conductive diaphragm and a conductive backplate are formed within the dielectric, with a sacrificial portion of the dielectric between them. A first recess is formed, which extends through the dielectric to an upper surface of the conductive diaphragm. A second recess is formed, which extends through the substrate and dielectric to a lower surface of the conductive backplate. The sacrificial layer is removed to create an air gap between the conductive diaphragm and the conductive backplate. The air gap joins the first and second recesses to form a cavity that extends continuously through the dielectric and the substrate. The present disclosure is also directed to the semiconductor structure of the MEMS microphone resulting from the manufacturing process.

Abstract translation: 一些实施例涉及将微机电系统（MEMS）麦克风的MEMS电容器和集成电路（IC）组合到单个基板上的制造工艺。 在器件衬底上形成电介质。 导电隔膜和导电背板形成在电介质内，电介质的牺牲部分在它们之间。 形成第一凹部，其延伸穿过电介质到导电隔膜的上表面。 形成第二凹槽，其延伸穿过基板和电介质到导电背板的下表面。 去除牺牲层以在导电隔膜和导电背板之间产生气隙。 空气间隙连接第一和第二凹部以形成连续延伸通过电介质和基底的空腔。 本公开还涉及由制造过程产生的MEMS麦克风的半导体结构。