公开(公告)号：US09666624B2

公开(公告)日：2017-05-30

申请号：US15093285

申请日：2016-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/18

Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate having a front surface and a back surface, and an interconnection structure formed over the front surface. The image-sensor device also includes a radiation-sensing region in the semiconductor substrate. The image-sensor device further includes an isolation structure adjacent to the radiation-sensing region. The isolation structure includes a trench extends from the back surface, and a negatively charged film extends along an interior surface of the trench.

公开(公告)号：US12278250B2

公开(公告)日：2025-04-15

申请号：US17321909

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Feng-Chi Hung ,  Shyh-Fann Ting

IPC: H01L27/146

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

公开(公告)号：US11908878B2

公开(公告)日：2024-02-20

申请号：US17327996

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1464 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14685

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

公开(公告)号：US11769791B2

公开(公告)日：2023-09-26

申请号：US17308381

申请日：2021-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Sheng Chu ,  Dun-Nian Yaung ,  Yu-Cheng Tsai ,  Meng-Hsien Lin ,  Ching-Chung Su ,  Jen-Cheng Liu ,  Wen-De Wang ,  Guan-Hua Chen

IPC: H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L28/75 ,  H01L28/87 ,  H01L28/88 ,  H01L28/92 ,  H01L29/66181 ,  H01L29/945 ,  H01L28/40

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

公开(公告)号：US11596800B2

公开(公告)日：2023-03-07

申请号：US16901884

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L25/00 ,  H01L27/06 ,  H01L27/146 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  A61N1/39

Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

公开(公告)号：US11502121B2

公开(公告)日：2022-11-15

申请号：US16909024

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ying Chen ,  Min-Feng Kao ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Dun-Nian Yaung

IPC: H01L27/146

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

公开(公告)号：US11437420B2

公开(公告)日：2022-09-06

申请号：US16733433

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Chi Hung ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wei Chuang Wu ,  Yen-Yu Chen ,  Chih-Kuan Yu

IPC: H01L27/146

Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

公开(公告)号：US11322481B2

公开(公告)日：2022-05-03

申请号：US16902539

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US11289455B2

公开(公告)日：2022-03-29

申请号：US16898613

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20220084908A1

公开(公告)日：2022-03-17

申请号：US17177660

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Wei Chuang Wu ,  Shih Kuang Yang ,  Hsing-Chih Lin ,  Jen-Cheng Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance