公开(公告)号：US20070138582A1

公开(公告)日：2007-06-21

申请号：US11312619

申请日：2005-12-20

Applicant: Peter Nystrom ,  Nancy Jia ,  Kee Ryu

Inventor： Peter Nystrom ,  Nancy Jia ,  Kee Ryu

IPC: H01L29/84

CPC classification number: B81C1/00801 ,  B41J2/14 ,  B41J2/16 ,  B41J2/1626 ,  B41J2/1639 ,  B41J2002/043 ,  B81B2201/052 ,  B81C2201/0109 ,  B81C2201/0133 ,  B81C2201/014

Abstract: This describes a starting structure and method for forming a micro-mechanical device. These devices have several uses in both government and commercial applications. The starting structure can be sold or supplied to others who will then make a final product, or it can be used directly to make a final product. An appropriate use of this starting structure is to make deformable devices useful in an inkjet printing device.

Abstract translation: 这描述了用于形成微机械装置的起始结构和方法。 这些设备在政府和商业应用中都有多种用途。 起始结构可以出售或提供给随后制造最终产品的其他人，或者可以直接用于制造最终产品。 适当地使用该起始结构是使可变形装置在喷墨打印装置中有用。

公开(公告)号：US07176545B2

公开(公告)日：2007-02-13

申请号：US10766629

申请日：2004-01-27

Applicant: Glenn J Leedy

Inventor： Glenn J Leedy

IPC: H01L31/00

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20070019923A1

公开(公告)日：2007-01-25

申请号：US11491389

申请日：2006-07-21

Applicant: Teruo Sasagawa ,  Clarence Chui ,  Manish Kothari ,  SuryaPrakash Ganti ,  Jeffrey Sampsell ,  Chun-Ming Wang

Inventor： Teruo Sasagawa ,  Clarence Chui ,  Manish Kothari ,  SuryaPrakash Ganti ,  Jeffrey Sampsell ,  Chun-Ming Wang

IPC: G02B6/00

CPC classification number: G02B26/0841 ,  B81B2201/042 ,  B81B2203/0307 ,  B81C1/00595 ,  B81C2201/014 ,  G02B26/001

Abstract: A microelectromechanical systems device having support structures formed of sacrificial material surrounded by a protective material. The microelectromechanical systems device includes a substrate having an electrode formed thereon. Another electrode is separated from the first electrode by a cavity and forms a movable layer, which is supported by support structures formed of a sacrificial material.

Abstract translation: 具有由保护材料包围的牺牲材料形成的支撑结构的微机电系统装置。 微机电系统装置包括其上形成有电极的基板。 另一电极通过空腔与第一电极分离，并形成可移动层，该可移动层由牺牲材料形成的支撑结构支撑。

公开(公告)号：US20060240583A1

公开(公告)日：2006-10-26

申请号：US11113554

申请日：2005-04-25

Applicant: William Baney ,  Dan Chilcott

Inventor： William Baney ,  Dan Chilcott

IPC: H01L21/00

CPC classification number: B81C1/00158 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/019 ,  G01L9/0042

Abstract: A technique for manufacturing silicon structures includes etching a cavity into a first side of an epitaxial wafer. A thickness of an epitaxial layer is selected, based on a desired depth of the etched cavity and a desired membrane thickness. The first side of the epitaxial wafer is then bonded to a first side of a handle wafer. After thinning the epitaxial wafer until only the epitaxial layer remains, desired circuitry is formed on a second side of the remaining epitaxial layer, which is opposite the first side of the epitaxial wafer.

Abstract translation: 制造硅结构的技术包括将空腔蚀刻到外延晶片的第一侧。 基于蚀刻空腔的期望深度和期望的膜厚度来选择外延层的厚度。 然后将外延晶片的第一侧接合到处理晶片的第一侧。 在使外延晶片变薄直到只剩余外延层之后，在与外延晶片的第一侧相对的剩余外延层的第二侧上形成所需的电路。

公开(公告)号：US20060231521A1

公开(公告)日：2006-10-19

申请号：US11107083

申请日：2005-04-15

Applicant: Dan Chilcott

Inventor： Dan Chilcott

IPC: C23F1/00

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0135 ,  B81C2201/014 ,  B81C2201/017

Abstract: A technique for manufacturing a micro-electro mechanical structure includes a number of steps. Initially, a cavity is formed into a first side of a handling wafer, with a sidewall of the cavity forming a first angle greater than about 54.7 degrees with respect to a first side of the handling wafer at an opening of the cavity. Then, a bulk etch is performed on the first side of the handling wafer to modify the sidewall of the cavity to a second angle greater than about 90 degrees, with respect to the first side of the handling wafer at the opening of the cavity. Next, a second side of a second wafer is bonded to the first side of the handling wafer.

Abstract translation: 微电子机械结构的制造技术包括多个步骤。 最初，空腔形成处理晶片的第一侧，空腔的侧壁在空腔的开口处相对于处理晶片的第一侧形成大于约54.7度的第一角度。 然后，在处理晶片的第一侧上执行体蚀刻，以将空腔的侧壁相对于处理晶片在空腔开口处的第一侧大于约90度的第二角度进行修改。 接下来，将第二晶片的第二面接合到处理晶片的第一侧。

公开(公告)号：US20060189144A1

公开(公告)日：2006-08-24

申请号：US11063108

申请日：2005-02-22

Applicant: John Krawczyk ,  Andrew McNees ,  Christopher Money ,  Girish Patil ,  David Rhine ,  Karthik Vaideeswaran

Inventor： John Krawczyk ,  Andrew McNees ,  Christopher Money ,  Girish Patil ,  David Rhine ,  Karthik Vaideeswaran

IPC: H01L21/30

CPC classification number: H01L21/0332 ,  B81B2203/0353 ,  B81C1/00531 ,  B81C1/00619 ,  B81C2201/0132 ,  B81C2201/014 ,  H01L21/0334 ,  H01L21/3081 ,  H01L21/3083

Abstract: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop material. The first layer is a relatively soft etch stop material. A second layer is applied to the first layer on the back side of the substrate to provide a composite etch stop layer. The second layer is a relatively hard etch stop material. The substrate is etched from a side opposite the back side of the substrate to provide a slot in the substrate.

Abstract translation: 使用深反应离子蚀刻工艺蚀刻半导体衬底以在衬底中产生通孔或槽（以下称为“槽”）的工艺。 该方法包括将第一层作为第一蚀刻停止材料施加到衬底的背面。 第一层是相对软的蚀刻停止材料。 将第二层施加到衬底的背面上的第一层以提供复合蚀刻停止层。 第二层是相对硬的蚀刻停止材料。 从与衬底的背面相对的一侧蚀刻衬底，以在衬底中提供槽。

公开(公告)号：US07052623B1

公开(公告)日：2006-05-30

申请号：US09581663

申请日：1999-09-22

Applicant: Volker Becker ,  Franz Laermer ,  Andrea Schilp

Inventor： Volker Becker ,  Franz Laermer ,  Andrea Schilp

IPC: H01L21/00

CPC classification number: H01L21/30655 ,  B81C1/00571 ,  B81C2201/014

Abstract: A method is proposed for etching a first silicon layer (15) that is provided with an etching mask (10) for defining lateral recesses (21). In a first plasma etching process, trenches (21′) are produced in the region of the lateral recesses (21) by anisotropic etching. The first etching process comes virtually to a standstill as soon as a separating layer (12, 14, 14′, 16), buried between the first silicon layer (15) and a further silicon layer (17), is reached. This separating layer is thereupon etched through in exposed regions (23, 23′) by a second etching process. A subsequent third etching process then etches the further silicon layer (17, 17′). In this manner, free-standing structures for sensor elements can be produced in a simple process which is completely compatible with the method steps in IC integration technology.

Abstract translation: 提出了一种蚀刻第一硅层（15）的方法，第一硅层（15）设置有用于限定横向凹槽（21）的蚀刻掩模（10）。 在第一等离子体蚀刻工艺中，通过各向异性蚀刻在横向凹槽（21）的区域中产生沟槽（21'）。 一旦达到掩埋在第一硅层（15）和另一硅层（17）之间的分离层（12,14,14'，16），第一蚀刻工艺实际上就停滞了。 然后通过第二蚀刻工艺在曝光区域（23,23'）中蚀刻该分离层。 接下来的第三蚀刻工艺然后蚀刻另外的硅层（17,17'）。 以这种方式，可以以与IC集成技术中的方法步骤完全兼容的简单过程来生产传感器元件的独立结构。

公开(公告)号：US07049165B2

公开(公告)日：2006-05-23

申请号：US10725874

申请日：2003-12-02

Applicant: Takahiro Oguchi

Inventor： Takahiro Oguchi

IPC: H01L21/302

CPC classification number: G01C19/5719 ,  B81B2201/025 ,  B81C1/00579 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/159

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching.

Abstract translation: 通过干式蚀刻中的蚀刻停止层，使用通过元件基板的贯通孔干蚀刻形成传感器元件的外力检测传感器的制造方法。

公开(公告)号：US20050221528A1

公开(公告)日：2005-10-06

申请号：US11129541

申请日：2005-05-13

Applicant: Mike Bruner

Inventor： Mike Bruner

IPC: B81C1/00 ,  B81B3/00 ,  B81B7/00 ,  H01L21/46 ,  H02N1/00 ,  H03H9/24

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

公开(公告)号：US20050199973A1

公开(公告)日：2005-09-15

申请号：US11053115

申请日：2005-02-07

Applicant: Hubert Benzel ,  Gerhard Lammel

Inventor： Hubert Benzel ,  Gerhard Lammel

IPC: B81B3/00 ,  B81C1/00 ,  G01L9/00 ,  H01L21/00 ,  H01L29/84

CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/014 ,  G01L9/0042 ,  G01L9/0054

Abstract: In a method for manufacturing a micromechanical semiconductor component, e.g., a pressure sensor, a locally limited, buried, and at least partially oxidized porous layer is produced in a semiconductor substrate. A cavity is subsequently produced in the semiconductor substrate from the back, directly underneath the porous first layer, using a trench etch process. The porous first layer is used as a stop layer for the trench. Thin diaphragms having a low thickness tolerance may thus be produced for differential pressure measurement.

Abstract translation: 在制造微机电半导体部件的方法中，例如压力传感器，在半导体衬底中产生局部限制的，掩埋的和至少部分氧化的多孔层。 随后，使用沟槽蚀刻工艺，在半导体衬底中从后部直接在多孔第一层下方产生空腔。 多孔第一层用作沟槽的停止层。 因此可以产生具有低厚度公差的薄膜，用于差压测量。