公开(公告)号：US20210098049A1

公开(公告)日：2021-04-01

申请号：US16942278

申请日：2020-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Shih-Hao Lin

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/11 ,  H01L21/475

摘要： Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US10607846B2

公开(公告)日：2020-03-31

申请号：US16103025

申请日：2018-08-14

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Hidehiko Karasaki ,  Noriyuki Matsubara ,  Atsushi Harikai ,  Hidefumi Saeki

IPC分类号： H01L21/00 ,  H01L21/3065 ,  B23K26/0622 ,  H01L21/02 ,  H01L21/475 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78

摘要： Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.

公开(公告)号：US10566344B2

公开(公告)日：2020-02-18

申请号：US15983726

申请日：2018-05-18

申请人： SK hynix Inc.

发明人： Woo Sung Moon ,  Do Youn Kim

IPC分类号： H01L21/02 ,  H01L27/11582 ,  H01L21/311 ,  H01L27/11565 ,  H01L21/027 ,  H01L21/475 ,  H01L21/768

摘要： A method of manufacturing a three-dimensional semiconductor device, the method comprising: forming a stack structure; patterning channel holes using light transmission holes of an exposure mask; forming cell plugs penetrating the stack structure; and patterning wave-type slits using light transmission holes of the exposure mask, wherein the step of patterning holes further includes sequentially stacking a first mask layer and a first photoresist layer on the stack structure, and exposing the first photoresist layer by light transmitted through the exposure mask.

公开(公告)号：US10553814B2

公开(公告)日：2020-02-04

申请号：US15525500

申请日：2015-12-17

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Yi Kong ,  Junhao Liu ,  Hongwei Xue ,  Qingsong Xu ,  Lu Liu

IPC分类号： G02F1/1339 ,  H01L51/52 ,  H01L27/12 ,  H01L21/70 ,  H01L21/475

摘要： An array substrate, a display panel, a display device, a method for manufacturing the array substrate and a method for manufacturing the display panel are provided. The array substrate includes a base substrate, and an organic layer and a passivation layer arranged above the base substrate. The base substrate includes a display region and a non-display region surrounding the display region. Each of the organic layer and the passivation layer is arranged in both the display region and the non-display region. A groove is arranged in the organic layer and the passivation layer in the non-display region, the groove penetrates the organic layer and the passivation layer and is of a closed pattern surrounding the display region. The groove is to be filled with a sealing material.

公开(公告)号：US10217704B1

公开(公告)日：2019-02-26

申请号：US15794403

申请日：2017-10-26

申请人： National Technology & Engineering Solutions of Sandia, LLC

发明人： Randy J. Shul ,  Jeffry J. Sniegowski ,  Kurt W. Larson ,  William A. Zortman

IPC分类号： H01L21/768 ,  H01L23/522 ,  G06F17/50 ,  H01L21/311 ,  H01L21/48 ,  H01L23/498 ,  H01L21/475

摘要： Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.

公开(公告)号：US10204802B2

公开(公告)日：2019-02-12

申请号：US15569759

申请日：2017-03-22

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Zhidong Yuan

IPC分类号： H01L21/48 ,  H01L21/02 ,  G09G3/20 ,  H01L21/4757 ,  H01L21/475 ,  H01L29/417 ,  H01L21/77 ,  H01L21/768 ,  H01L21/47

摘要： The present disclosure provides a method of forming a via hole, an array substrate and a method of forming the same and a display device. The method of forming a via hole includes: forming a pattern of a first via hole and a pattern of an upper-part etched structure of a second via hole simultaneously on a base substrate through a first patterning process by using a first mask; forming a pattern of the second hole in a region corresponding to the formed pattern of the upper-part etched structure of the second via hole through a second patterning process by using a second mask.

公开(公告)号：US10192746B1

公开(公告)日：2019-01-29

申请号：US15665183

申请日：2017-07-31

申请人： GLOBALFOUNDRIES, Inc.

发明人： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

摘要： A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US20190006236A1

公开(公告)日：2019-01-03

申请号：US16045073

申请日：2018-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/475 ,  H01L23/528 ,  H01L21/4757 ,  H01L29/06

摘要： A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

公开(公告)号：US09991135B2

公开(公告)日：2018-06-05

申请号：US15521246

申请日：2014-10-31

申请人： SHENZHEN GRADUATE SCHOOL, PEKING UNIVERSITY

发明人： Shengdong Zhang ,  Yang Shao ,  Xiang Xiao ,  Xin He

IPC分类号： H01L21/473 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/475 ,  H01L21/443

CPC分类号： H01L21/473 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/28 ,  H01L21/443 ,  H01L21/475 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.

公开(公告)号：US09954112B2

公开(公告)日：2018-04-24

申请号：US14995562

申请日：2016-01-14

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/475 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/67 ,  C23C16/40 ,  C23C16/455 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

摘要： A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.