Systems and techniques for timing mismatch reduction

    公开(公告)号:US12021531B2

    公开(公告)日:2024-06-25

    申请号:US17895826

    申请日:2022-08-25

    CPC classification number: H03K3/0232 G01R31/31727 H03K3/014 H03K3/0315

    Abstract: Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

    System and method to control memory error detection with automatic disabling

    公开(公告)号:US12019512B2

    公开(公告)日:2024-06-25

    申请号:US17829576

    申请日:2022-06-01

    CPC classification number: G06F11/1004

    Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

    Energy efficient heat pump with valve system and counterflow arrangement

    公开(公告)号:US12018871B2

    公开(公告)日:2024-06-25

    申请号:US18306819

    申请日:2023-04-25

    Inventor: Rong Yu

    CPC classification number: F25B41/26 F25B13/00 F25B2313/02743 F25B2313/0276

    Abstract: An energy efficient heat pump for a heating, ventilation, and air conditioning (HVAC) system includes a vapor compression circuit, a heat exchanger of the vapor compression circuit configured to place a working fluid in a heat exchange relationship with an air flow directed across the heat exchanger, and a valve system of the vapor compression circuit. The valve system is adjustable between a first configuration and a second configuration, the heat pump is configured to operate in a cooling mode with the valve system in the first configuration and in a heating mode with the valve system in the second configuration, and the valve system is configured to direct the working fluid into the heat exchanger to place the working fluid in a counterflow heat transfer arrangement with the air flow in the first configuration and in the second configuration.

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