公开(公告)号：US11906451B2

公开(公告)日：2024-02-20

申请号：US17448081

申请日：2021-09-20

Applicant: Nova Ltd. ,  GLOBALFOUNDRIES U.S. INC.

Inventor： Wei Ti Lee ,  Heath A. Pois ,  Mark Klare ,  Cornel Bozdog ,  Alok Vaid

IPC: G01N23/2273 ,  H01L21/66 ,  G01B11/06 ,  G01B15/02 ,  G01N23/2208 ,  G01N23/223

CPC classification number: G01N23/2273 ,  G01B11/06 ,  G01B15/02 ,  G01N23/223 ,  G01N23/2208 ,  H01L22/12 ,  G01N2223/305 ,  G01N2223/61 ,  G01N2223/633

Abstract: A monitoring system and method are provided for determining at least one property of an integrated circuit (IC) comprising a multi-layer structure formed by at least a layer on top of an underlayer. The monitoring system receives measured data comprising data indicative of optical measurements performed on the IC, data indicative of x-ray photoelectron spectroscopy (XPS) measurements performed on the IC and data indicative of x-ray fluorescence spectroscopy (XRF) measurements performed on the IC. An optical data analyzer module analyzes the data indicative of the optical measurements and generates geometrical data indicative of one or more geometrical parameters of the multi-layer structure formed by at least the layer on top of the underlayer. An XPS data analyzer module analyzes the data indicative of the XPS measurements and generates geometrical and material related data indicative of geometrical and material composition parameters for said layer and data indicative of material composition of the underlayer. An XRF data analyzer module analyzes the data indicative of the XRF measurements and generates data indicative of amount of a predetermined material composition in the multi-layer structure. A data interpretation module generates combined data received from analyzer modules and processes the combined data and determines the at least one property of at least one layer of the multi-layer structure.

公开(公告)号：US20240045140A1

公开(公告)日：2024-02-08

申请号：US18378788

申请日：2023-10-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng BIAN ,  Ajey Poovannummoottil JACOB ,  Steven M. SHANK

IPC: G02B6/122 ,  G02B6/125 ,  G02B1/00

CPC classification number: G02B6/1225 ,  G02B6/125 ,  G02B1/002 ,  G02B1/005 ,  G02B2006/12061

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.

公开(公告)号：US20240038882A1

公开(公告)日：2024-02-01

申请号：US18487115

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： VIBHOR JAIN ,  JOHNATAN AVRAHAM KANTAROVSKY ,  MARK DAVID LEVY ,  EPHREM GEBRESELASIE ,  YVES NGU ,  SIVA P. ADUSUMILLI

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/66431 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/435

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20240038881A1

公开(公告)日：2024-02-01

申请号：US18487114

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： VIBHOR JAIN ,  JOHNATAN AVRAHAM KANTAROVSKY ,  MARK DAVID LEVY ,  EPHREM GEBRESELASIE ,  YVES NGU ,  SIVA P. ADUSUMILLI

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/66431 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/435

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20240038653A1

公开(公告)日：2024-02-01

申请号：US17816493

申请日：2022-08-01

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： EeJan Khor ,  Ramasamy Chockalingam ,  Juan Boon Tan ,  Pannirselvam Somasuntharam

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L28/60

Abstract: A structure for a capacitor is provided. The structure includes a first metal electrode, such as a copper electrode, having at least one dielectric region, such as a dielectric, therein. A first dielectric layer is on the first metal electrode, and a second metal electrode is on the first dielectric layer. At least one via is on the second metal electrode. Each via is over the at least one dielectric region in the first metal electrode.

公开(公告)号：US20240036087A1

公开(公告)日：2024-02-01

申请号：US17815961

申请日：2022-07-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Indranil Som ,  Vaibhav Anantrai Ruparelia ,  Kuppireddy Vasudeva Reddy

IPC: G01R19/04

CPC classification number: G01R19/04

Abstract: Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch.

公开(公告)号：US11889701B2

公开(公告)日：2024-01-30

申请号：US17237886

申请日：2021-04-22

Applicant: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG

Inventor： Tarek Ali ,  Konstantin H. J. Mertens ,  Maximilian W. Lederer ,  David J. Lehninger ,  Konrad Seidel

IPC: H01L21/00 ,  H10B53/30 ,  H01L49/02 ,  H01L29/78 ,  H01L29/51 ,  H10B51/30

CPC classification number: H10B53/30 ,  H01L28/60 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/30

Abstract: Memory cells include various versions of a capacitor structure including a polarization retention member. Each polarization retention member includes an antiferroelectric layer over a ferroelectric layer. The antiferroelectric layer, among other layers, can be tailored to customize the hysteresis loop shape, and the coercive electric field required to change polarization of the memory cell. Metal electrodes, and/or dielectric or metallic interlayers may also be employed to tailor the hysteresis. The memory cells can include FeRAMs or FeFETs. The memory cells provide a lower coercive electric field requirement compared to conventional ferroelectric memory cells, enhanced reliability, and require minimum changes to integrate into current integrated circuit fabrication processes.

公开(公告)号：US11888051B2

公开(公告)日：2024-01-30

申请号：US16869851

申请日：2020-05-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jiacheng Lei ,  Lawrence Selvaraj Susai ,  Joseph James Jerry

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/201

CPC classification number: H01L29/7783 ,  H01L29/201 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Structures for a high-electron-mobility transistor and methods of forming a structure for a high-electron-mobility transistor. The high-electron-mobility transistor has a first semiconductor layer, a second semiconductor layer adjoining the first semiconductor layer along an interface, a gate electrode, and a source/drain region. An insulator region is provided in the first semiconductor layer and the second semiconductor layer. The insulator region extends through the interface at a location laterally between the gate electrode and the source/drain region.

公开(公告)号：US11886021B2

公开(公告)日：2024-01-30

申请号：US17705911

申请日：2022-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/02 ,  G02B6/122 ,  G02B6/13 ,  G02B6/30 ,  G02B6/42 ,  G02B6/12

CPC classification number: G02B6/4203 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/305

Abstract: Photonics structures including a slotted waveguide and methods of fabricating such photonics structures. The photonics structure includes a slotted waveguide having a first waveguide core and a second waveguide core laterally positioned adjacent to the first waveguide core. The first waveguide core is separated from the second waveguide core by a slot. The photonics structure further includes a metamaterial structure having a plurality of elements separated by a plurality of gaps and a dielectric material in the plurality of gaps. The metamaterial structure and the slot of the slotted waveguide are positioned with an overlapping arrangement.

公开(公告)号：US20240028811A1

公开(公告)日：2024-01-25

申请号：US17813344

申请日：2022-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A process design kit (PDK) is supplied to a layout design tool. The PDK includes parameterized cells (Pcells) adapted to cause the layout design tool to automatically add labels to device layouts in the graphic design system (GDS) file that is being created by the layout design tool. Each corresponding label lists parameters used when creating the corresponding device layout. The GDS file is receive back from the layout design tool. The parameters from the labels is applied to corresponding ones of the Pcells within the PDK to create a device verification layout for each of the device layouts in the GDS file. Each of the device layouts in the GDS file is compared to a corresponding device verification layout. The device layouts within the GDS file that fail to match the corresponding device verification layout are thereby identified.