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    Methods of forming MOS transistors having buried gate electrodes therein
    111.
    发明申请
    Methods of forming MOS transistors having buried gate electrodes therein 有权
    在其中形成具有掩埋栅电极的MOS晶体管的方法

    公开(公告)号：US20060105529A1

    公开(公告)日：2006-05-18

    申请号：US11246401

    申请日：2005-10-07

    Applicant: Sang-Hyeon Lee

    Inventor： Sang-Hyeon Lee

    IPC: H01L21/336

    CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/78645 ,  H01L29/78648

    Abstract: Methods of forming field effect transistors having buried gate electrodes include the steps of forming a semiconductor substrate having a sacrificial gate electrode buried beneath a surface of the semiconductor substrate and then removing the sacrificial gate electrode to define a gate electrode cavity beneath the surface. The gate electrode cavity is lined with a gate insulating layer. The lined gate electrode cavity is filled with a first insulated gate electrode. A second insulated gate electrode is also formed on a portion of the semiconductor substrate extending opposite the first insulated gate electrode so that a channel region of the field effect transistor extends between the first and second insulated gate electrodes. Source and drain regions are also formed adjacent opposite ends of the first and second insulated gate electrodes.

    Abstract translation: 形成具有掩埋栅电极的场效应晶体管的方法包括以下步骤：形成半导体衬底，该半导体衬底具有掩埋在半导体衬底表面之下的牺牲栅电极，然后去除牺牲栅电极以在表面下方限定栅极电极腔。 栅极电极腔内衬有栅极绝缘层。 衬里的栅电极腔填充有第一绝缘栅电极。 第二绝缘栅电极也形成在半导体衬底的与第一绝缘栅极相对延伸的部分上，使得场效应晶体管的沟道区在第一和第二绝缘栅电极之间延伸。 源极和漏极区域也形成在第一和第二绝缘栅电极的相对端附近。

    Dram devices having an increased density layout
    113.
    发明申请
    Dram devices having an increased density layout 失效
    具有增加密度布局的戏剧装置

    公开(公告)号：US20050269615A1

    公开(公告)日：2005-12-08

    申请号：US11015993

    申请日：2004-12-17

    Applicant: Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    Inventor： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/02 ,  H01L29/74

    CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

    Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

    Abstract translation: DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

    Method for preparing zno nanopowder
    115.
    发明申请
    Method for preparing zno nanopowder 审中-公开
    制备zno纳米粉末的方法

    公开(公告)号：US20050095194A1

    公开(公告)日：2005-05-05

    申请号：US10497985

    申请日：2002-12-07

    Applicant: Sung Park ,  Ju-Hyeon Lee ,  Kang-Ryul Lee

    Inventor： Sung Park ,  Ju-Hyeon Lee ,  Kang-Ryul Lee

    IPC: C01G9/02 ,  C02F1/30 ,  C02F1/32 ,  C02F1/72

    CPC classification number: B82Y30/00 ,  C01G9/02 ,  C01P2002/72 ,  C01P2004/04 ,  C02F1/32 ,  C02F1/725 ,  C02F2305/10 ,  Y02W10/37

    Abstract: Disclosed is a method of preparing ZnO nanopowder according to a non-equilibrium synthetic process, comprising adding an organic substance containing an amine group or a carboxyl group as a fuel material to an aqueous solution having Zn2+ and (NO3) ions to prepare a mixed solution, and heating the resulting solution with agitation. The method is advantageous in that the ZnO nanopowder has excellent valuable metal recovery and harmful organic substance decomposition efficiency, and the highly pure ZnO nanopowder with nano-sized particles is prepared in commercial quantities.

    Abstract translation: 公开了根据非平衡合成方法制备ZnO纳米粉末的方法，包括将含有胺基或羧基的有机物质作为燃料材料添加到具有Zn 2+的水溶液中，以及 （NO 3 N 3）离子以制备混合溶液，并在搅拌下加热所得溶液。 该方法的优点在于ZnO纳米粉末具有极好的有价值的金属回收率和有害有机物质的分解效率，并以商品数量制备了具有纳米尺寸颗粒的高纯ZnO纳米粉末。

    Method of forming self-aligned contact pads of non-straight type semiconductor memory device
    116.
    发明申请
    Method of forming self-aligned contact pads of non-straight type semiconductor memory device 有权
    形成非直型半导体存储器件的自对准接触焊盘的方法

    公开(公告)号：US20050070080A1

    公开(公告)日：2005-03-31

    申请号：US10944151

    申请日：2004-09-16

    Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

    IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

    CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

    Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如棒型，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光致抗蚀剂图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

    Signal processor and apparatus and method for testing same
    117.
    发明申请
    Signal processor and apparatus and method for testing same 有权

    公开(公告)号：US20050030209A1

    公开(公告)日：2005-02-10

    申请号：US10852937

    申请日：2004-05-25

    Applicant: Sang-Hyeon Lee

    Inventor： Sang-Hyeon Lee

    IPC: G01R31/316 ,  G01R31/00 ,  G01R31/28 ,  H03M1/10 ,  H03M1/12 ,  H03M3/00

    CPC classification number: H03M3/378 ,  H03M3/43 ,  H03M3/454

    Abstract: An apparatus for testing a signal processor includes an integrator and a control section. The integrator switches an input signal in response to a first clock signal to allow the input signal to be charged in at least one capacitive element, and outputs the charged input signal in response to a second clock signal. The control section is coupled to the integrator, and provides the integrator with a control signal to discharge the capacitive elements based on a level of the input signal at a previous part of a test mode. The time required for testing the signal processor is reduced.

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