公开(公告)号：US07456912B2

公开(公告)日：2008-11-25

申请号：US10983071

申请日：2004-11-05

Applicant: Yih-Jun Wong ,  Horng-Long Cheng ,  Yu-Wu Wang

Inventor： Yih-Jun Wong ,  Horng-Long Cheng ,  Yu-Wu Wang

IPC: G02F1/136

CPC classification number: G02F1/133553 ,  G02F1/136227

Abstract: An organic thin film transistor array substrate including a substrate divided into an LCD region and an OTFT region; a first dielectric layer formed on the substrate in the LCD region and having a first uneven portion; an organic semiconducting layer formed on the substrate in the OTFT region; a gate, source, and drain formed in the OTFT region, wherein the source and drain are in contact with the organic semiconducting layer to form a channel between the source and drain; and a pixel electrode formed on the first uneven portion of the first dielectric layer in the LCD region.

Abstract translation: 一种有机薄膜晶体管阵列基板，包括分为LCD区域和OTFT区域的基板; 形成在所述LCD区域的所述基板上并具有第一凹凸部的第一电介质层; 形成在OTFT区域的基板上的有机半导体层; 在OTFT区域中形成的栅极，源极和漏极，其中源极和漏极与有机半导体层接触以在源极和漏极之间形成沟道; 以及形成在LCD区域中的第一电介质层的第一凹凸部上的像素电极。

公开(公告)号：US20080263492A1

公开(公告)日：2008-10-23

申请号：US11833119

申请日：2007-08-02

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

IPC: G06F17/50

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

Abstract translation: 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

公开(公告)号：US20080258228A1

公开(公告)日：2008-10-23

申请号：US11833128

申请日：2007-08-02

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

公开(公告)号：US20080020533A1

公开(公告)日：2008-01-24

申请号：US11490012

申请日：2006-07-20

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Harry Chuang

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract translation: 公开了一种具有改善的源极/漏极结的半导体器件和用于制造器件的方法。 优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域 形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。 在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度和45度之间。 另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

公开(公告)号：US20070128744A1

公开(公告)日：2007-06-07

申请号：US11190525

申请日：2005-07-27

Applicant: James Tour ,  Long Cheng ,  Paul Franzon ,  David Neckeshi

Inventor： James Tour ,  Long Cheng ,  Paul Franzon ,  David Neckeshi

IPC: H01L21/00 ,  H01L23/58 ,  H01L51/40

CPC classification number: H01L51/0049 ,  B82Y10/00 ,  B82Y30/00 ,  G11C13/0014 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/16 ,  H01L51/0595

Abstract: An assembly of a NanoCell comprising a disordered array of metallic islands interlinked with molecules between metallic input/output leads and with disordered arrays of molecules and Au islands is disclosed. The NanoCell may function both as a memory device that is programmable post-fabrication. The assembled NanoCells exhibit reproducible switching behavior and at least two types of memory effects at room temperature. The switch-type memory is characteristic of a destructive read while the conductivity-type memory features a nondestructive read. Both types of s memory effects are stable for more than a week at room temperature and bit level ratios (0:1) of the conductivity-type memory have been observed to be as high as 104:1 and reaching 106:1 upon ozone treatment which likely destroys extraneous leakage pathways. The invention demonstrates the efficacy of a disordered

Abstract translation: 公开了包含与金属输入/输出引线之间的分子相互连接并且具有无序分子阵列和Au岛的金属岛的无序阵列的纳米晶体组件。 NanoCell可以兼作可编程后期制作的存储器件。 组装的NanoCells在室温下表现出可重现的切换行为和至少两种记忆效应。 开关型存储器是具有破坏性读取的特征，而导电型存储器具有非破坏性读取。 两种类型的记忆效应在室温下稳定超过一周，并且已经观察到导电型存储器的位电平比（0：1）高达10：1 并在臭氧处理时达到10 6：1，这可能会破坏外部泄漏路径。 本发明证明了无序的

公开(公告)号：US07157351B2

公开(公告)日：2007-01-02

申请号：US10850747

申请日：2004-05-20

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

IPC: H01L21/76

CPC classification number: H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02307 ,  H01L21/31662 ,  H01L21/76224

Abstract: A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

Abstract translation: 一种在表面特别是硅表面上清洗和形成氧化膜的方法。 表面最初被清洁，然后暴露于臭氧蒸汽，这在表面上形成氧化膜。 该方法在STI（浅沟槽隔离）结构的制造中在沟槽表面上形成预衬垫氧化膜特别有用。

公开(公告)号：US20060220181A1

公开(公告)日：2006-10-05

申请号：US11097743

申请日：2005-04-01

Applicant: Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Yuan Lin

Inventor： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Yuan Lin

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/417

Abstract: A dummy region varactor for improving a CMP process and improving electrical isolation from active areas and a method for forming the same, the varactor including a semiconductor substrate having a dummy region said dummy region including a first well region having a first polarity; shallow trench isolation (STI) structures disposed in the dummy region defining adjacent mesa regions comprising first, second, and third mesa regions; a second well region having a second polarity underlying the first mesa region having the second polarity to form a PN junction interface; wherein said second and third mesa regions having the first polarity are formed adjacent either side of said first mesa region.

公开(公告)号：US07026644B2

公开(公告)日：2006-04-11

申请号：US10990210

申请日：2004-11-16

Applicant: Horng-Long Cheng ,  Wei-Yang Chou ,  Yih-Jun Wong ,  Yu-Wu Wang ,  Cheng-Chung Lee

Inventor： Horng-Long Cheng ,  Wei-Yang Chou ,  Yih-Jun Wong ,  Yu-Wu Wang ,  Cheng-Chung Lee

IPC: H01L29/004

CPC classification number: H01L51/0541 ,  G02F1/133555 ,  G02F1/13378 ,  G02F1/1368 ,  H01L27/28 ,  H01L51/0545

Abstract: The invention provides an organic thin film transistor array substrate, comprising: a substrate, having a liquid crystal display area and an organic thin film transistor area; a pixel electrode, formed on the substrate in the LCD area; a first alignment film, formed on the pixel electrode; a second alignment film, formed on the substrate in the OTFT area; an organic semiconductor layer, formed on the second alignment film, wherein the organic semiconductor layer is aligned along the direction of the second alignment film; and a gate, a source and a drain, formed in the OTFT area, wherein the source and the drain are in contact with the organic semiconductor layer and a channel is formed between the source and the drain.

Abstract translation: 本发明提供一种有机薄膜晶体管阵列基板，包括：具有液晶显示区域和有机薄膜晶体管区域的基板; 形成在LCD面上的基板上的像素电极; 形成在像素电极上的第一取向膜; 形成在OTFT区域的基板上的第二取向膜; 形成在所述第二取向膜上的有机半导体层，其中所述有机半导体层沿着所述第二取向膜的方向排列; 以及形成在OTFT区域中的栅极，源极和漏极，其中源极和漏极与有机半导体层接触并且在源极和漏极之间形成沟道。

公开(公告)号：US07026195B2

公开(公告)日：2006-04-11

申请号：US10851376

申请日：2004-05-21

Applicant: Chung-Long Cheng ,  Kong-Beng Thei

Inventor： Chung-Long Cheng ,  Kong-Beng Thei

IPC: H01L21/00 ,  H01L21/302

CPC classification number: H01L29/785 ,  H01L21/32139 ,  H01L29/42384 ,  H01L29/66795

Abstract: A method for forming a FIN-FET device employs a blanket planarizing layer formed upon a blanket topographic gate electrode material layer. The blanket planarizing layer is patterned and employed as a mask layer for patterning the blanket topographic gate electrode material layer to form a gate electrode. Since the blanket planarizing layer is formed as a planarizing layer, a photoresist layer formed thereupon is formed with enhanced resolution. As a result, the gate electrode is also formed with enhanced resolution. A resulting FIN-FET structure has the patterned planarizing layer formed in an inverted “U” shape upon the gate electrode.

Abstract translation: 用于形成FIN-FET器件的方法使用形成在覆盖的地形栅电极材料层上的覆盖平坦化层。 图案化覆盖层平坦化层并用作掩模层，用于图案化覆盖层形成的栅电极材料层以形成栅电极。 由于覆盖平坦化层形成为平坦化层，所以在其上形成的光致抗蚀剂层以更高的分辨率形成。 结果，栅电极也形成了增强的分辨率。 所得到的FIN-FET结构具有在栅电极上以倒U形形成的图案化平坦化层。

公开(公告)号：US20050125875A1

公开(公告)日：2005-06-16

申请号：US10734926

申请日：2003-12-13

Applicant: Yuan-Long Cheng

Inventor： Yuan-Long Cheng

IPC: A42B1/04 ,  A41D1/00

CPC classification number: A42B1/046 ,  A41D2200/20

Abstract: A cloth hood is made by punching a flexible cloth into a pair of bilaterally symmetrical twin pieces and stitching them together. The cloth hood includes a gap formed at a position corresponding to that of each eye in respective pieces, a jutting portion below each gap, a recess portion defined at somewhere below the jutting portion and along the peripheral stitch line of the cloth hood, an extension end defined below the recess portion, another recess portion arranged at a position almost exactly opposite to the mentioned recess portion and top and bottom ends of the cloth hood shaped in arc style. As the cloth hood can be closely and flexibly attached onto a user's head, it is possible to prevent hair or scalp bits from being dropped to the floor without incurring any discomfort to the user.

Abstract translation: 通过将柔性布冲压成一对双向对称的双件并将它们拼接在一起而制成布罩。 布罩包括形成在相应于每个眼睛的每个眼睛的位置处的间隙，每个间隙下方的突出部分，限定在突出部分的下方并沿着布罩的周边线迹的凹部，延伸部 端部限定在凹部下方，另一个凹部布置在几乎完全相对于所述凹部的位置，并且布罩的顶端和底端形成为弧形。 由于布罩可以紧密地和柔性地附接到使用者的头部上，所以可以防止头发或头皮屑落到地板上，而不会对使用者造成不适。