公开(公告)号：US20160173003A1

公开(公告)日：2016-06-16

申请号：US14903994

申请日：2014-08-18

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stephane Monfray ,  Christophe Maitre ,  Olga Kokshagina ,  Thomas Skotnicki ,  Ulrich Soupremanien

IPC: H02N1/08

CPC classification number: H02N1/08 ,  B81B3/0021 ,  B81B3/0024 ,  B81B2203/053 ,  F01K5/02 ,  H02N1/006

Abstract: A power conversion device includes an enclosure containing one or more drops of a liquid. A capacitive electret transducer is coupled to the enclosure. In response to applied heat at a heating surface, the liquid vaporizes and then condenses on a flexible membrane of the capacitive electret transducer. The flexible membrane is displaced in response to the vaporization-condensation and the capacitive electret transducer generates an output current.

Abstract translation: 电力转换装置包括包含一滴或多滴液体的外壳。 电容驻极体换能器耦合到外壳。 响应于加热表面处的加热，液体蒸发然后在电容驻极体换能器的柔性膜上冷凝。 柔性膜响应于汽化冷凝而移位，并且电容驻极体换能器产生输出电流。

公开(公告)号：US09337302B2

公开(公告)日：2016-05-10

申请号：US13933379

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L29/66477 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.

Abstract translation: 集成电路具有FET，具有FET的UTBOX层铅垂，具有FET的栅极和沟道的第一掺杂铅垂的下层接地层，第一和第二下层半导体元件，两者均与漏极或源极接触，电极分别接触 接地平面和第一元件，一个具有第一掺杂并且连接到第一电压，另一个具有第一掺杂并且连接到不同于第一掺杂的第二偏置电压，具有第二掺杂和铅垂的半导体阱与 第一接地平面和两个元件，第一沟槽将第一FET与集成电路的其它部件隔离并延伸穿过该阱进入阱，第二和第三沟槽将FET与电极隔离，并延伸至小于 平面/井界面。

公开(公告)号：US20160104729A1

公开(公告)日：2016-04-14

申请号：US14840680

申请日：2015-08-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Laurent Favennec ,  Didier Dutartre ,  Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/11 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.

Abstract translation: 一种制造钉扎光电二极管的方法，包括：在第二导电类型的衬底上形成光子转换到第一导电类型的电荷的区域; 用第二导电类型的重掺杂绝缘体层涂覆所述区域; 和退火以确保掺杂剂从重掺杂绝缘体层扩散。

公开(公告)号：US09312408B2

公开(公告)日：2016-04-12

申请号：US14738529

申请日：2015-06-12

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre

IPC: H01L31/0232 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/042

CPC classification number: H01L31/02327 ,  H01L27/1461 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14689 ,  H01L31/0232 ,  H01L31/0352 ,  H01L31/042

Abstract: The disclosure relates to an image sensor comprising a substrate region in a semiconductor material; an active layer in contact with the substrate region; and a photodiode array formed in the active layer. The substrate region has a doping level such that the resistivity of the substrate region is less than 6 mOhm·cm.

Abstract translation: 本公开涉及一种包括半导体材料中的衬底区域的图像传感器; 与所述衬底区域接触的有源层; 以及形成在有源层中的光电二极管阵列。 衬底区域具有使得衬底区域的电阻率小于6mOhm·cm的掺杂水平。

公开(公告)号：US09299865B2

公开(公告)日：2016-03-29

申请号：US14464898

申请日：2014-08-21

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Laurent Frey ,  Sebastien Jouan ,  Salim Boutami

IPC: H01L29/06 ,  H01L31/062 ,  H01L27/14 ,  H01L31/107 ,  H01L31/0352 ,  G01T1/24 ,  H01L31/0232 ,  H01L27/146

CPC classification number: H01L31/035236 ,  G01T1/248 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/02327 ,  H01L31/107

Abstract: A SPAD-type photodiode has a semiconductor substrate with a light-receiving surface. A lattice formed of interlaced strips made of a first material covers the light receiving surface. The lattice includes lattice openings with lateral walls covered by a spacer made of a second material. Then first and second materials have different optical indices, and further each optical index is less than or equal to the substrate optical index. A pitch of the lattice is of the order of a magnitude of an operating wavelength of the photodiode. The first and second materials are transparent at that operating wavelength. The lattice is made of a conductive material electrically coupled to an electrical connection node (for example, a bias voltage node).

Abstract translation: SPAD型光电二极管具有具有受光面的半导体基板。 由第一材料制成的交错条形成的格子覆盖光接收表面。 格子包括具有被由第二材料制成的间隔物覆盖的侧壁的格子开口。 然后第一和第二材料具有不同的光学指数，并且每个光学指数还小于或等于基底光学指数。 晶格的间距是光电二极管的工作波长大小的数量级。 第一和第二材料在该工作波长下是透明的。 晶格由电耦合到电连接节点（例如，偏压节点）的导电材料制成。

公开(公告)号：US20160087594A1

公开(公告)日：2016-03-24

申请号：US14734514

申请日：2015-06-09

Applicant: STMicroelectronics SA

Inventor： Laurent Chabert

IPC: H03F3/19 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03F3/45282 ,  G01S7/03 ,  H03D7/1433 ,  H03D7/1458 ,  H03F1/0205 ,  H03F1/0261 ,  H03F3/19 ,  H03F3/193 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45372 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2200/91 ,  H03F2203/30015 ,  H03F2203/45081 ,  H03F2203/45112 ,  H03F2203/45154 ,  H03F2203/45288 ,  H04B1/06

Abstract: An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

Abstract translation: 电子设备包括具有类AB类型的放大器末级的跨阻放大器级和耦合在频率转置级的输出和放大器端级的输入之间的前置放大级。 自偏置共模控制级被配置为偏置前置放大器级。 前置放大器级由具有响应于自偏置共模控制级偏置的有源负载的差分放大器形成。

公开(公告)号：US20160078963A1

公开(公告)日：2016-03-17

申请号：US14844442

申请日：2015-09-03

Applicant: STMicroelectronics SA

Inventor： Stephane Lacouture ,  Joel Damiens

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C5/145 ,  G11C17/16 ,  G11C17/165

Abstract: For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold. When the threshold is exceeded, indicative of successful programming of the antifuse memory cell, the programming mode is terminated.

Abstract translation: 为了编程反熔丝存储器，在编程模式下评估存储器的功耗。 将功耗与阈值进行比较。 当超过阈值时，指示反熔丝存储器单元的成功编程，编程模式被终止。

公开(公告)号：US20160056192A1

公开(公告)日：2016-02-25

申请号：US14929077

申请日：2015-10-30

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Robert MANOUVRIER ,  Pascal FONTENEAU ,  Xavier MONTAGNER

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/4236

Abstract: The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.

公开(公告)号：US20160047986A1

公开(公告)日：2016-02-18

申请号：US14804629

申请日：2015-07-21

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain CHANTRE ,  Sébastien CREMER

IPC: G02B6/136 ,  H01S5/026 ,  G02B6/42 ,  G02B6/12 ,  G02B6/132 ,  H01S5/343 ,  H01S5/02

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/4257 ,  G02B2006/121 ,  G02B2006/12121 ,  H01S5/0085 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/343

Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Abstract translation: 制造包括硅层上的光子分量和由III-V族材料制成的激光的集成电路的方法包括提供位于位于支撑体上的第一绝缘层上的硅层。 第一沟槽被蚀刻穿过硅层并在第一绝缘层上停止，并且第一沟槽被氮化硅层覆盖。 第二沟槽被蚀刻通过硅层的一部分，并且第一和第二沟槽用平坦化的氧化硅填充。 该方法还包括去除支撑体和第一绝缘层，以及在硅层的后表面上接合包括III-V族异质结构的晶片。

公开(公告)号：US09235667B2

公开(公告)日：2016-01-12

申请号：US13852162

申请日：2013-03-28

Applicant: STMicroelectronics SA

Inventor： Jean-Robert Manouvrier

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A model for simulating the electrical behavior of a thyristor includes a model of an NPN bipolar transistor whose emitter forms the cathode of the thyristor and the base forms a low-side control terminal of the thyristor, and a model of a PNP bipolar transistor whose emitter forms the anode of the thyristor and the base forms a high-side control terminal of the thyristor, the collector of the PNP transistor being connected to the low-side control terminal and the collector of the NPN transistor being connected to the high-side control terminal. The transistor models are present a small signal behavior over the entire range of anode currents of the thyristor, whereby the transistor models exhibit a gain drop when the anode current exits the small signal range.

Abstract translation: 用于模拟晶闸管的电气行为的模型包括其发射极形成晶闸管的阴极并且基极形成晶闸管的低侧控制端的NPN双极晶体管的模型，以及PNP双极晶体管的模型，其发射极 形成晶闸管的阳极，基极形成晶闸管的高边控制端子，PNP晶体管的集电极连接到低侧控制端子，NPN晶体管的集电极连接到高侧控制 终奌站。 晶体管模型在晶闸管的整个阳极电流范围内呈现小的信号行为，由此当阳极电流退出小信号范围时，晶体管模型呈现增益下降。