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    ARTIFICIAL NEURAL NETWORK PROCESSING METHODS AND SYSTEMS
    112.
    发明公开
    ARTIFICIAL NEURAL NETWORK PROCESSING METHODS AND SYSTEMS 审中-公开

    公开(公告)号：US20240273344A1

    公开(公告)日：2024-08-15

    申请号：US18434549

    申请日：2024-02-06

    Applicant: STMicroelectronics International N.V.

    Inventor： Filippo NACCARI ,  Angelo BOSCO

    IPC: G06N3/047

    CPC classification number: G06N3/047

    Abstract: A processing device includes memory circuitry having stored therein a set of weight values and a threshold value and instructions which, when executed in the processing device, cause the processing device to apply a first artificial neural network (ANN) processing to a set of sensing signals, producing as a result a set of compressed representations of the sensing signals. The first ANN processing is trained to produce the set of compressed representations using a set of training signals distributed according to a set of training classes having an integer number L of classes. The instructions further cause the processing device to configure weight values of a plurality of computing units of a set of ANN processing circuits as a function of a set of weight values.

    MEMORY MANAGEMENT METHOD TO SAVE ENERGY
    114.
    发明公开
    MEMORY MANAGEMENT METHOD TO SAVE ENERGY 审中-公开

    公开(公告)号：US20240256154A1

    公开(公告)日：2024-08-01

    申请号：US18420263

    申请日：2024-01-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Michael GIOVANNINI

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0673

    Abstract: A system includes a memory formed by memory units accessible in write mode and in read mode. Each memory unit includes an array of memory cells and a peripheral circuit of access to the memory cells. Each memory unit is configurable in a first operating mode and a second operating mode. The array of memory cells are set in the first operating mode and the second operating modes to retain data until a subsequent powering off of the memory unit. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode. A controller configures any memory unit of the memory having undergone no write or read access for a determined time period to be in the second operating mode.

    SENSOR UNIT WITH ON-DEVICE LEARNING AND ANOMALY DETECTION
    115.
    发明公开
    SENSOR UNIT WITH ON-DEVICE LEARNING AND ANOMALY DETECTION 审中-公开

    公开(公告)号：US20240255386A1

    公开(公告)日：2024-08-01

    申请号：US18161674

    申请日：2023-01-30

    Applicant: STMicroelectronics International N.V.

    Inventor： Federico RIZZARDINI ,  Lorenzo BRACCO

    IPC: G01M99/00 ,  G06N20/00

    CPC classification number: G01M99/005 ,  G06N20/00

    Abstract: A sensor unit is coupled to a machine and configured to detect anomalous behavior of the machine. The sensor unit includes a low power microcontroller that learns to recognize a plurality of operations of the machine. The sensor unit generates mean vector and inverse of a Cholesky decomposition matrix for each operation. During a detection mode the sensor unit computes a Mahalanobis distance for each feature vector, mean vector and first matrix. The sensor unit detects anomalous behavior or classifies the operation of the machine based on the Mahalanobis distances.

    MACHINE LEARNING FRAME FILTERING
    117.
    发明公开
    MACHINE LEARNING FRAME FILTERING 审中-公开

    公开(公告)号：US20240248570A1

    公开(公告)日：2024-07-25

    申请号：US18158932

    申请日：2023-01-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Ta-Jung Tsai

    IPC: G06F3/044

    CPC classification number: G06F3/0446

    Abstract: According to an embodiment, a regression analysis is performed on a subset of a dataset, where the subset of the dataset corresponds to inputs from a first row of a matrix of sensors at a time instant k. The regression analysis generates a set of coefficients. A filter transform, to be applied on the subset of the dataset, is determined based on a comparison between the set of coefficients and threshold values. The filter transform can be one of an infinite impulse response (IIR) filter transform, a first-order filter transform, or a second-order filter transform. Once the filter transform is determined, it is applied to the subset of the dataset to generate a first output matrix.

    RESET CIRCUITRY PROVIDING INDEPENDENT RESET SIGNAL FOR TRACE AND DEBUG LOGIC
    119.
    发明公开
    RESET CIRCUITRY PROVIDING INDEPENDENT RESET SIGNAL FOR TRACE AND DEBUG LOGIC 审中-公开

    公开(公告)号：US20240241811A1

    公开(公告)日：2024-07-18

    申请号：US18155204

    申请日：2023-01-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Avneep Kumar GOYAL ,  Amritanshu ANAND ,  Satinder Singh MALHI

    IPC: G06F11/36 ,  G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/3656 ,  G06F11/0772 ,  G06F11/1441

    Abstract: In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.

    Static random access memory supporting a single clock cycle read-modify-write operation
    120.
    发明授权
    Static random access memory supporting a single clock cycle read-modify-write operation 有权

    公开(公告)号：US12040013B2

    公开(公告)日：2024-07-16

    申请号：US17861384

    申请日：2022-07-11

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar Verma ,  Harsh Rawat

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/418

    Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

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