公开(公告)号：US20080061330A1

公开(公告)日：2008-03-13

申请号：US11531290

申请日：2006-09-13

申请人： Gwo-Yuh Shiau ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Shih-Chi Fu ,  Chia-Shiung Tsai

发明人： Gwo-Yuh Shiau ,  Ming-Chyi Liu ,  Yuan-Chih Hsieh ,  Shih-Chi Fu ,  Chia-Shiung Tsai

IPC分类号： H01L31/062

CPC分类号： H01L27/14687 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14831

摘要： Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer.

摘要翻译： 提供了图像传感器装置及其制造方法。 图像传感器装置的示例性实施例包括支撑衬底。 在支撑衬底上形成钝化结构。 在钝化结构上形成互连结构。 第一半导体层形成在互连结构上，具有第一和第二表面，其中第一和第二表面是相对的表面。 至少一个感光装置从其第一表面形成在第一半导体层之上/之中。 滤色器层从其第二表面形成在第一半导体层上。 在滤色器层上形成至少一个微透镜。

公开(公告)号：US20070096230A1

公开(公告)日：2007-05-03

申请号：US11610760

申请日：2006-12-14

申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

IPC分类号： H01L43/00 ,  H01L29/82

CPC分类号： H01L43/12 ,  H01L27/228

摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

摘要翻译： 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

公开(公告)号：US20070048965A1

公开(公告)日：2007-03-01

申请号：US11291880

申请日：2005-12-01

申请人： Yuan-Chih Hsieh ,  Chung-Yi Yu ,  Tsung-Hsun Huang ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

发明人： Yuan-Chih Hsieh ,  Chung-Yi Yu ,  Tsung-Hsun Huang ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

IPC分类号： H01L21/76

CPC分类号： H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14687

摘要： An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.

摘要翻译： 图像传感器装置包括半导体衬底和衬底上的多个像素。 在像素上方形成蚀刻停止层，其厚度小于约600埃。 图像传感器装置还包括覆盖在蚀刻停止层上的层间电介质（ILD）。 蚀刻停止层的折射率小于约2，消光系数小于约0.1。

公开(公告)号：US20070023816A1

公开(公告)日：2007-02-01

申请号：US11191437

申请日：2005-07-27

申请人： Yuan-Hung Liu ,  Shih-Chi Fu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Shih-Chi Fu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： An EEPROM flash memory device having a floating gate electrode enabling a reduced erase voltage and method for forming the same, the floating gate electrode including an outer edge portion comprising multiple charge transfer pointed tips.

摘要翻译： 一种具有能够实现降低的擦除电压的浮动栅电极的EEPROM闪存器件及其形成方法，该浮栅电极包括包含多个电荷转移尖端的外边缘部分。

公开(公告)号：US07153755B2

公开(公告)日：2006-12-26

申请号：US11044813

申请日：2005-01-26

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/10894 ,  H01L27/11

摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

摘要翻译： 提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。 该方法包括以下步骤：形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层（BARC）层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

公开(公告)号：US20050274968A1

公开(公告)日：2005-12-15

申请号：US10982978

申请日：2004-11-05

申请人： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

发明人： Ching-Sen Kuo ,  Feng-Jia Shiu ,  Gwo-Yuh Shiau ,  Jieh-Jang Chen ,  Shih-Chi Fu ,  Chien Tseng ,  Chia-Shiung Tsai ,  Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chih-Ta Wu ,  Chi-Hsin Lo

IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/22 ,  H01L29/227 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L33/00 ,  H01L47/02

CPC分类号： H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687

摘要： An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.

摘要翻译： 图像传感器包括双微透镜结构，其外部微透镜在内部微透镜上对准，两个微透镜在相应的光电传感器上对准。 内部或外部微透镜可以通过甲硅烷基化方法形成，其中光致抗蚀剂材料的反应性部分与含硅试剂反应。 内部或外部微透镜可以通过介电材料的步骤蚀刻形成，该步骤蚀刻工艺包括一系列交替蚀刻步骤，其包括各向异性蚀刻步骤和使图案化光致抗蚀剂横向后退的蚀刻步骤。 可以使用随后的各向同性蚀刻工艺来平滑蚀刻的台阶结构并形成光滑的透镜。 热稳定和感光的聚合物/有机材料也可用于形成永久的内镜片或外镜片。 感光材料被涂覆，然后使用光刻图案化，回流，然后固化以形成永久性透镜结构。

公开(公告)号：US20050079672A1

公开(公告)日：2005-04-14

申请号：US10685127

申请日：2003-10-14

申请人： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

发明人： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/32139 ,  H01L27/115

摘要： A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

摘要翻译： 一种分裂栅FET字线电极结构及其形成方法，包括改进的多晶硅蚀刻工艺，包括提供包括第一裸露多晶硅部分和相邻氧化物部分的半导体晶片工艺表面; 在所述暴露的多晶硅部分上形成第一氧化物层; 在第一暴露的多晶硅部分和相邻的氧化物部分上覆盖多晶硅层; 在所述多晶硅层上形成硬掩模层; 执行多步反应离子蚀刻（RIE）工艺以蚀刻穿过硬掩模层并蚀刻穿过多晶硅层的厚度部分，以形成与具有向上突出的外部多晶硅栅栏部分的氧化物部分相邻的第二多晶硅部分; 使所述半导体晶片工艺表面与HF水溶液接触; 并且执行下游等离子体蚀刻工艺以去除多晶硅栅栏部分。

公开(公告)号：US06869837B1

公开(公告)日：2005-03-22

申请号：US10758316

申请日：2004-01-15

申请人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Yeur-Luen Tu ,  Chin-Ta Wu ,  Tsung-Hsun Huang ,  Hsiu Ouyang ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.

摘要翻译： 一种制造字线间隔物的方法，包括以下步骤。 提供了具有形成在其上的初始分离栅闪存结构的衬底。 导电层形成在衬底和初生分裂栅极闪存结构之上。 所述导电层具有：上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。 在导电层之上形成双层氧化物层，并且在导电层的上部上具有更大的厚度。 将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层，以暴露导电层的下面部分。 然后蚀刻：将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分，以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物 结构体。

公开(公告)号：US06764967B2

公开(公告)日：2004-07-20

申请号：US10264489

申请日：2002-10-05

申请人： Vincent Pai ,  Kuo-Chi Tu ,  Chung-Wei Chang ,  Chia-Shiung Tsai ,  Chun-Yao Chen

发明人： Vincent Pai ,  Kuo-Chi Tu ,  Chung-Wei Chang ,  Chia-Shiung Tsai ,  Chun-Yao Chen

IPC分类号： H01L2131

CPC分类号： H01L21/28238 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31675 ,  Y10S438/906

摘要： A method for forming a silicon dioxide layer over a silicon substrate including providing a substrate having exposed silicon portions; and, forming a silicon dioxide layer over the exposed silicon portions according to an oxide formation process including contacting the exposed silicon portions with an oxidizing solution comprising water and ozone.

摘要翻译： 一种在硅衬底上形成二氧化硅层的方法，包括提供具有暴露的硅部分的衬底; 以及根据氧化物形成过程在暴露的硅部分上形成二氧化硅层，包括使暴露的硅部分与包含水和臭氧的氧化溶液接触。

公开(公告)号：US06656847B1

公开(公告)日：2003-12-02

申请号：US09431240

申请日：1999-11-01

申请人： Huan Just Lin ,  Chia-Shiung Tsai

发明人： Huan Just Lin ,  Chia-Shiung Tsai

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/3185 ,  H01L21/32137 ,  H01L21/76802

摘要： The invention provides a method for etching silicon nitride selective to titanium silicide and fabricating multi-level contact openings on a quartermicron device using a two step etch process. The process begins by providing a substrate having thereover a silicon nitride hard mask at one level and a titanium silicide layer at another level wherein the silicon nitride hard mask and the titanium silicide region have an oxide layer thereover. In a first etch step, the oxide layer is patterned to form a first contact opening and a second contact opening. The first contact opening stops on the silicon nitride hard mask and the second contact opening stops on the titanium silicide region. In a second etch step the silicon nitride hard mask is etched through in the first contact opening using an etch selective to titanium silicide. The etch comprises CH2F2 and O2 at a ratio of CH2F2 to O2 of between about 2 and 4.

摘要翻译： 本发明提供了一种用于蚀刻对硅化钛有选择性的氮化硅并且使用两步蚀刻工艺在四分之一器件上制造多层接触开口的方法。 该工艺首先提供一层具有氮化硅硬掩模和另一层的硅化钛层的衬底，其中氮化硅硬掩模和硅化钛区域之间具有氧化物层。 在第一蚀刻步骤中，图案化氧化物层以形成第一接触开口和第二接触开口。 第一接触开口在氮化硅硬掩模上停止，并且第二接触开口在硅化钛区域上停止。 在第二蚀刻步骤中，使用对硅化钛的选择性蚀刻，在第一接触开口中蚀刻氮化硅硬掩模。 蚀刻包括CH 2 F 2和O 2，CH 2 F 2与O 2的比例在约2和4之间。