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公开(公告)号：US08102695B2
公开(公告)日：2012-01-24
申请号：US12430067
申请日：2009-04-25
申请人： Kazuo Ono , Riichiro Takemura , Tomonori Sekiguchi
发明人： Kazuo Ono , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C7/18 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/00 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C13/02 , G11C2013/0078 , G11C2213/79
摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.
摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关来并行提供两个电流路径。
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公开(公告)号：US20110110150A1
公开(公告)日：2011-05-12
申请号：US13008893
申请日：2011-01-18
IPC分类号： G11C11/00
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高度可靠的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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公开(公告)号：US20110103136A1
公开(公告)日：2011-05-05
申请号：US12939069
申请日：2010-11-03
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。
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公开(公告)号：US07933141B2
公开(公告)日：2011-04-26
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译： 在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。 本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。 监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过以下方式适当地执行对存储器单元的重新加载操作： 全局局部感测放大器。 因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。
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公开(公告)号：US07903449B2
公开(公告)日：2011-03-08
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译： 半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。 每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。 电容器的第一电极连接到存储单元中的晶体管。 虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。 虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。 虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。
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公开(公告)号：US20110044092A1
公开(公告)日：2011-02-24
申请号：US12916499
申请日：2010-10-30
申请人： KAZUO ONO , Riichiro Takemura , Tomonori Sekiguchi
发明人： KAZUO ONO , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C13/0011 , G11C13/0069 , G11C16/3468 , G11C2013/0066 , G11C2013/009 , G11C2213/52 , G11C2213/79
摘要： A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.
摘要翻译： 电阻变化存储器减少了编程之后的电阻值的不均匀性，使得可以以高速度对存储器单元执行重写操作。 参考电阻与电阻变化存储单元串联连接，传感器放大器检测存储单元和参考电阻之间的中间节点处的电位是否超过给定阈值电压，以便基于 检测结果。
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公开(公告)号：US20090323399A1
公开(公告)日：2009-12-31
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko KAJIGAYA , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko KAJIGAYA , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24 , G11C8/08 , H01L27/108
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译： 半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。 每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。 电容器的第一电极连接到存储单元中的晶体管。 虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。 虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。 虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。
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公开(公告)号：US20090180341A1
公开(公告)日：2009-07-16
申请号：US12314860
申请日：2008-12-17
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
CPC分类号： G11C7/22 , G11C7/04 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C7/222 , G11C11/4094 , H01L27/0207 , H01L27/108 , H01L27/10897 , H03K5/15066
摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).
摘要翻译： 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。
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119.发明申请公开(公告)号：US20070297257A1
公开(公告)日：2007-12-27
申请号：US11889902
申请日：2007-08-17
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C7/02
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of the capacitor and a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.
摘要翻译： 动态RAM包含多个动态存储单元，每个动态存储单元包括具有作为选择端子的栅极集合的MOSFET，作为输入/输出端子的一个源极和漏极组，以及连接到电容器的存储节点的另一个源极和漏极 以及电容器，分别连接到多个动态存储单元的选择端子的多个字线，分别连接到多个动态存储单元的输入/输出端子的多个互补位线对，以及读出放大器 阵列包括多个锁存电路，其分别放大互补位线对之间的电压差，以便从每对输入/输出端子彼此相反的方向延伸。 电源线以网格形式提供，包括字驱动器上方的一部分。
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公开(公告)号：US07310256B2
公开(公告)日：2007-12-18
申请号：US11134476
申请日：2005-05-23
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。
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