公开(公告)号：US10153253B2

公开(公告)日：2018-12-11

申请号：US15357233

申请日：2016-11-21

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Eng Huat Goh ,  Min Suet Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H05K1/11 ,  H05K3/30 ,  H05K3/36 ,  H05K1/14

Abstract: A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

公开(公告)号：US10085342B2

公开(公告)日：2018-09-25

申请号：US15376872

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim ,  Chin Lee Kuan ,  Howe Yin Loo

IPC: H01L21/00 ,  H01L23/48 ,  H05K1/16 ,  H01F17/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H05K1/165 ,  H01F17/0033 ,  H01F41/046 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19042 ,  H05K2201/086

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

公开(公告)号：US10083922B2

公开(公告)日：2018-09-25

申请号：US15359926

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Chin Lee Kuan ,  Eng Huat Goh ,  Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

公开(公告)号：US20180168043A1

公开(公告)日：2018-06-14

申请号：US15376872

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim ,  Chin Lee Kuan ,  Howe Yin Loo

IPC: H05K1/16 ,  H01F17/02 ,  H01F17/00 ,  H01F41/04 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/046 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/645 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19042 ,  H05K2201/086

Abstract: A microelectronic device incorporating an air core inductor having one or more inserts to provide efficiency of the inductor are described. One or more inserts having a selected permeability may be placed within regions defined by coils of the air core inductor. The inserts can be formed of a solid material of the selected permeability or such a material can be applied to other structures, such as circuit components. Other embodiments may be described and/or claimed.

公开(公告)号：US20180097056A1

公开(公告)日：2018-04-05

申请号：US15282504

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Han Kung Chua ,  Min Suet Lim ,  Hoay Tien Teoh

IPC: H01L49/02

CPC classification number: H01L28/75

Abstract: A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

公开(公告)号：US20170359893A1

公开(公告)日：2017-12-14

申请号：US15182091

申请日：2016-06-14

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Fern Nee Tan ,  Khang Choong Yong ,  Jiun Hann Sir

IPC: H05K1/02 ,  H01G4/008 ,  H01L23/00 ,  H01G4/12 ,  H01L21/48 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H05K1/09 ,  H01L23/498

CPC classification number: H05K1/0231 ,  H01G4/1209 ,  H01G4/228 ,  H01G4/33 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/19041 ,  H01L2924/19102 ,  H05K1/141 ,  H05K2201/10015 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Capacitive interconnects and processes for fabricating the capacitive interconnects are provided. In some embodiments, the capacitive interconnect includes first metal layers, second metal layers; and dielectric layers including a dielectric layer that intercalates a first metal layer of the first metal layers and a second metal layer of the second metal layers. Such layers can be assembled in a nearly concentric arrangement, where the dielectric layer abuts the first metal layer and the second metal layer abuts the dielectric layer. In addition, the capacitive interconnect can include a first electrode electrically coupled to at least one of the first metal layers, and a second electrode electrically coupled to at least one of the second metal layers, the second electrode assembled opposite to the first electrode. The first electrode and the second electrode can include respective solder tops. The capacitive interconnects can be utilized in a semiconductor package, providing a compact assembly that can reduce the utilization of real estate in a board substrate onto which the semiconductor package is mounted.

公开(公告)号：USD773452S1

公开(公告)日：2016-12-06

申请号：US29539359

申请日：2015-09-14

Applicant: Intel Corporation

Designer： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

公开(公告)号：USD756349S1

公开(公告)日：2016-05-17

申请号：US29513077

申请日：2014-12-26

Applicant: Intel Corporation

Designer： Min Suet Lim ,  Bok Eng Cheah ,  Howe Yin Loo ,  Jackson Chung Peng Kong ,  Poh Tat Oh

公开(公告)号：US20160132077A1

公开(公告)日：2016-05-12

申请号：US14996568

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackon Chung Peng Kong ,  Poh Tat Oh

IPC: G06F1/16 ,  H05K5/02

CPC classification number: E05D3/06 ,  E05D11/0081 ,  G06F1/1615 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1662 ,  G06F1/1677 ,  G06F1/1681 ,  G06F1/3218 ,  G06F1/3265 ,  H05K5/0226 ,  Y02D10/153 ,  Y10T16/522 ,  Y10T16/533 ,  Y10T16/5475

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

公开(公告)号：US20160130849A1

公开(公告)日：2016-05-12

申请号：US14998225

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackon Chung Peng Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  E05D11/00 ,  G06F1/16

CPC classification number: E05D3/06 ,  E05D11/0081 ,  G06F1/1615 ,  G06F1/1616 ,  G06F1/1618 ,  G06F1/1662 ,  G06F1/1677 ,  G06F1/1681 ,  G06F1/3218 ,  G06F1/3265 ,  H05K5/0226 ,  Y02D10/153 ,  Y10T16/522 ,  Y10T16/533 ,  Y10T16/5475

Abstract: A personal computing device is provided with a first housing portion, a second housing portion, and a hinge joining the first housing portion to the second housing portion. The hinge is configured to allow the first housing portion to rotate substantially three-hundred-sixty degrees relative to the second housing portion. The hinge can be implemented as a plurality of interlinked parallel hinge segments, each hinge segment to rotate about a respective one of a plurality of parallel axes of the hinge to enable the rotation of the first housing portion.

Abstract translation: 个人计算设备设置有第一壳体部分，第二壳体部分和将第一壳体部分连接到第二壳体部分的铰链。 铰链被构造成允许第一壳体部分相对于第二壳体部分大致旋转三百六十度。 铰链可以实现为多个互连的平行铰链段，每个铰链段围绕铰链的多个平行轴线中的相应一个旋转，以使第一壳体部分能够旋转。