利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

163 条记录 (耗时 0.045 秒)

    METHOD AND STRUCTURE FOR INTEGRATING MIM CAPACITORS WITHIN DUAL DAMASCENE PROCESSING TECHNIQUES
    111.
    发明申请
    METHOD AND STRUCTURE FOR INTEGRATING MIM CAPACITORS WITHIN DUAL DAMASCENE PROCESSING TECHNIQUES 有权
    在双重加工加工技术中集成MIM电容器的方法与结构

    公开(公告)号：US20080064163A1

    公开(公告)日：2008-03-13

    申请号：US11531298

    申请日：2006-09-13

    申请人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

    发明人： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

    IPC分类号： H01L21/8242

    CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

    摘要翻译： 一种用于在双镶嵌加工中整合金属 - 绝缘体 - 金属（MIM）电容器的形成的方法包括在其中形成具有较低电容器电极和一个或多个下部金属线的较低层间电介质（ILD）层，所述ILD层具有第一 在其上形成介电覆盖层。 上ILD层形成在下ILD层上，并且通孔和上线结构限定在上ILD层内。 通孔和上线结构填充有平坦化层，然后在平坦化层上形成和图案化抗蚀剂层。 上部电容器电极结构限定在对应于抗蚀剂的去除部分的上部ILD层中。 通孔，上线结构和上电容器电极结构填充有导电材料，其中MIM电容器由下电容器电极，第一介电覆盖层和上电容器电极结构限定。

    CD uniformity of chrome etch to photomask process
    114.
    发明授权
    CD uniformity of chrome etch to photomask process 失效
    铬蚀刻到光掩模工艺的CD均匀性

    公开(公告)号：US07014959B2

    公开(公告)日：2006-03-21

    申请号：US10605801

    申请日：2003-10-28

    申请人： Shaun B. Crawford ,  Timothy J. Dalton ,  Thomas B. Faure ,  Cuc K. Huynh ,  Michelle L. Steen ,  Thomas M. Wagner

    发明人： Shaun B. Crawford ,  Timothy J. Dalton ,  Thomas B. Faure ,  Cuc K. Huynh ,  Michelle L. Steen ,  Thomas M. Wagner

    IPC分类号： G03F9/00 ,  G03C5/00

    CPC分类号： C23F4/00 ,  G03F1/80 ,  H01L21/0332 ,  H01L21/32136

    摘要： A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibits a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.

    摘要翻译： 通过在透明基底上沉积不透明层而形成光掩模。 抗蚀剂形成在不透明层上并选择性地图案化以暴露待被蚀刻出的不透明层的部分。 在干蚀刻步骤期间，光掩模暴露于在不透明层和抗蚀剂层之间具有等于或高于1.2:1的选择性的蚀刻剂气体混合物。 由于气体混合物的选择性，可以使用更薄的抗蚀剂膜，从而提高不透明层图案的分辨率和精度。 此外，由于对宏观负载效应和图案密度效应的敏感性降低，抗蚀剂的过蚀刻和不透明层的去抛光显着降低，从而实现了改进的蚀刻均匀性并因此改善了CD均匀性。

    Two-dimensional patterning employing self-assembled material
    116.
    发明授权
    Two-dimensional patterning employing self-assembled material 失效
    采用自组装材料的二维图案

    公开(公告)号：US08754400B2

    公开(公告)日：2014-06-17

    申请号：US13432036

    申请日：2012-03-28

    申请人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl J. Radens

    发明人： Timothy J. Dalton ,  Bruce B. Doris ,  Ho-Cheol Kim ,  Carl J. Radens

    IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/0338 ,  Y10T428/24612

    摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

    摘要翻译： 具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的第一纳米级自对准自组装嵌套线结构由第一层内的第一自组装嵌段共聚物形成。 第一层填充有填充材料，并且第二层沉积在包含第一纳米级嵌套线结构的第一层之上。 具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层内的第二自组装嵌段共聚物形成。 第一纳米级嵌套线结构和第二纳米级嵌套线结构的复合图案被转移到第一层下面的底层中以形成在两个方向上包含周期性的结构阵列。

    Three dimensional vertical E-fuse structures and methods of manufacturing the same
    118.
    发明授权
    Three dimensional vertical E-fuse structures and methods of manufacturing the same 失效
    三维垂直E熔丝结构及其制造方法

    公开(公告)号：US08232190B2

    公开(公告)日：2012-07-31

    申请号：US11865079

    申请日：2007-10-01

    申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

    发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

    IPC分类号： H01L21/44

    CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

    摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。