公开(公告)号：US20160240548A1

公开(公告)日：2016-08-18

申请号：US14623630

申请日：2015-02-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract translation: 存储器件包括多个含硅层，串选择线（SSL），串，位线，金属带状字线和多组多插头结构。 堆叠在基板上的含硅层。 SSL被设置在含硅层上并沿着第一方向延伸。 这些串垂直于含硅层和SSL并电连接到SSL。 位线布置在沿着第二方向延伸并电连接到弦的SSL上。 沿着第一方向布置多组多插头结构，以使串配置在两组相邻的多插头结构之间，其中每组多插头结构具有多个插头，每个插头对应于并与其连接 的含硅层。 每个金属带状字线连接到连接到相同的含硅层的插头。

公开(公告)号：US09401369B1

公开(公告)日：2016-07-26

申请号：US14623630

申请日：2015-02-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of multi-plugs structure. The silicon-containing layers stacked at a substrate. The SSLs are disposed on the silicon-containing layers and extend along a first direction. The strings are perpendicular to the silicon-containing layers and the SSLs and electrically connected to the SSLs. The bit lines are disposed on the SSLs extending along a second direction and electrically connected to the strings. The plural sets of multi-plugs structure are arranged along the first direction, so as to make the strings disposed between two adjacent sets of multi-plugs structure, wherein each set of multi-plugs structure has plural plugs each corresponding to and connected with one of the silicon-containing layers. Each of the metal strapped word lines is connected to the plugs that are connected to the identical silicon-containing layer.

Abstract translation: 存储器件包括多个含硅层，串选择线（SSL），串，位线，金属带状字线和多组多插头结构。 堆叠在基板上的含硅层。 SSL被设置在含硅层上并沿着第一方向延伸。 这些串垂直于含硅层和SSL并电连接到SSL。 位线布置在沿着第二方向延伸并电连接到弦的SSL上。 沿着第一方向布置多组多插头结构，以使串配置在两组相邻的多插头结构之间，其中每组多插头结构具有多个插头，每个插头对应于并与其连接 的含硅层。 每个金属带状字线连接到连接到相同的含硅层的插头。

公开(公告)号：US09391084B2

公开(公告)日：2016-07-12

申请号：US14309622

申请日：2014-06-19

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/792 ,  G11C16/10

CPC classification number: H01L27/11563 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory cell includes a gate, a channel material having a channel surface and a channel valence band edge, and a dielectric stack between the gate and the channel surface. The dielectric stack comprises a multi-layer tunneling structure on the channel surface, a first charge storage nitride layer on the multi-layer tunneling structure, a first blocking oxide layer on the first charge storage nitride layer, a second charge storage nitride layer on the first blocking dielectric layer, and a second blocking oxide layer on the second charge storage nitride layer. The multi-layer tunneling structure includes a first tunneling oxide layer, a first tunneling nitride layer on the first tunneling oxide layer, and a second tunneling oxide layer on the first tunneling nitride layer.

Abstract translation: 存储单元包括栅极，具有沟道表面和沟道价带边缘的沟道材料，以及栅极和沟道表面之间的介电堆叠。 电介质堆叠包括沟道表面上的多层隧道结构，多层隧道结构上的第一电荷存储氮化物层，第一电荷存储氮化物层上的第一阻挡氧化物层，第一电荷存储氮化物层 第一阻挡介质层和第二电荷存储氮化物层上的第二阻挡氧化物层。 多层隧道结构包括第一隧道氧化物层，第一隧道氧化物层上的第一隧穿氮化物层和第一隧穿氮化物层上的第二隧穿氧化物层。

公开(公告)号：US09324437B2

公开(公告)日：2016-04-26

申请号：US14446866

申请日：2014-07-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo Pin Chang ,  Chih-Shen Chang ,  Hang-Ting Lue

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/024 ,  G11C29/028

Abstract: Control transistors and memory cells within 3D NAND Flash memory arrays may both be created using the same technology, such as charge trapping structures, to simplify the fabrication process. However, the resulting control transistors may initially have higher variability in threshold voltages, when compared to traditional gate-oxide-based control transistors. Provided are exemplary techniques to trim control transistors to provide increased reliability and performance during array operation.

Abstract translation: 3D NAND闪存阵列内的控制晶体管和存储单元都可以使用相同的技术（如电荷俘获结构）来创建，以简化制造过程。 然而，与传统的基于栅极氧化物的控制晶体管相比，所得到的控制晶体管最初可能具有较高的阈值电压可变性。 提供了在阵列操作期间修整控制晶体管以提供增加的可靠性和性能的示例性技术。

公开(公告)号：US09269660B2

公开(公告)日：2016-02-23

申请号：US13772121

申请日：2013-02-20

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L23/50 ,  H01L23/522 ,  H01L23/48 ,  H01L27/112 ,  H01L21/768 ,  H01L27/02 ,  H01L27/115 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。

公开(公告)号：US09263143B2

公开(公告)日：2016-02-16

申请号：US14330106

申请日：2014-07-14

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue ,  Chen-Jun Wu

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/115

CPC classification number: G11C16/16 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.

Abstract translation: 一种三维（3D）存储器件的数据擦除方法，包括以下步骤。 首先，在擦除操作的第一阶段中，将第一电压施加到半导体通道的第一半导体通道，以擦除存储在第一半导体通道上限定的存储单元中的数据，并将第二电压施加到第二半导体通道 的半导体通道，其中第二半导体沟道与第一半导体沟道相邻。 然后，在擦除操作的第二阶段中，将第二电压施加到第一半导体沟道，并将第一电压施加到第二半导体沟道。

公开(公告)号：US09190467B2

公开(公告)日：2015-11-17

申请号：US14149873

申请日：2014-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  An-Chyi Wei ,  Hang-Ting Lue

IPC: H01L29/06 ,  H01L27/115 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/0603 ,  H01L27/11578 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7843

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，堆叠带状结构和拉伸材料带。 堆叠的带状结构垂直地形成在基板上，堆叠的带状结构具有压应力。 堆叠的带状结构包括多个导电条和多个绝缘条，并且导电条和绝缘条是交错的。 拉伸材料带形成在堆叠的带状结构上，拉伸材料带具有拉伸应力。

公开(公告)号：US20150194481A1

公开(公告)日：2015-07-09

申请号：US14149873

申请日：2014-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  An-Chyi Wei ,  Hang-Ting Lue

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/0603 ,  H01L27/11578 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7843

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，堆叠带状结构和拉伸材料带。 堆叠的带状结构垂直地形成在基板上，堆叠的带状结构具有压应力。 堆叠的带状结构包括多个导电条和多个绝缘条，并且导电条和绝缘条是交错的。 拉伸材料带形成在堆叠的带状结构上，拉伸材料带具有拉伸应力。

公开(公告)号：US09018047B2

公开(公告)日：2015-04-28

申请号：US14486901

申请日：2014-09-15

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: H01L21/82 ,  H01L23/52 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7923

Abstract: A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.

Abstract translation: 存储器件包括存储器单元的NAND串的阵列。 该装置包括由绝缘材料隔开的多个导体条叠层，包括导电条的至少底面，导电条的多个中间平面和导电条的顶面。 该装置包括在堆叠中的多个中间平面中的导电条的侧表面之间的交叉点的接口区域中的电荷存储结构以及多个位线结构的堆叠间半导体主体元件。 至少一个参考线结构正交布置在堆叠上，包括在导体条的底部平面与衬底之间的参考导体电连通的堆叠之间的垂直导电元件以及连接垂直导电元件的堆叠上的连接元件。 垂直导电元件具有比半导体主体元件更高的导电性。

公开(公告)号：US20150109844A1

公开(公告)日：2015-04-23

申请号：US14058328

申请日：2013-10-21

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: H01L27/105 ,  G11C7/14 ,  G11C5/06

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。