公开(公告)号：US20140246645A1

公开(公告)日：2014-09-04

申请号：US14276198

申请日：2014-05-13

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L27/24 ,  H01L45/00 ,  G11C5/02

CPC classification number: H01L45/1608 ,  G11C5/02 ,  G11C5/06 ,  G11C13/0004 ,  G11C2213/71 ,  H01L21/302 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165

Abstract: An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

Abstract translation: 非易失性存储单元的阵列包括多个垂直堆叠的非易失性存储单元层。 层分别包括第一多个水平取向的第一电极线和相对于第一电极线交叉的第二多个水平取向的第二电极线。 存储单元的个体包括第一电极线和第二电极线中的一个之间的交叉的一个以及其间的材料。 具体地说，与可编程材料串联的选择装置以及与可编程材料和选择装置之间串联的当前导电材料与第一和第二电极线中交叉的那些串联地提供。 材料和装置可以被定向成在限定的水平和垂直方向上的主要电流流动。 公开了方法和其他实现和方面。

公开(公告)号：US20140246642A1

公开(公告)日：2014-09-04

申请号：US14184142

申请日：2014-02-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.

Abstract translation: 本文描述了与相变单元结构相关联的方法和装置。 在一个或多个实施例中，形成相变单元结构的方法包括形成包括底电极的衬底突起，在衬底突起上形成相变材料，在相变材料上形成导电材料，以及去除部分 的导电材料和相变材料的一部分以形成封装的堆叠结构。

公开(公告)号：US20140217352A1

公开(公告)日：2014-08-07

申请号：US14251421

申请日：2014-04-11

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  John K. Zahurak

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

Abstract translation: 一些实施例包括在一对电极之间具有多个可编程材料结构的存储器单元。 可编程材料结构之一具有第一边缘，另一个可编程材料结构具有接触第一边缘的第二边缘。 一些实施例包括形成存储器单元阵列的方法。 第一可编程材料段形成在底部电极上。 第一可编程材料段沿第一轴线延伸。 第二可编程材料的线形成在第一可编程材料段上，并且形成为沿与第一轴相交的第二轴线延伸。 第二可编程材料线具有接触第一可编程材料段的上表面的下表面。 顶部电极线形成在第二可编程材料线上。

公开(公告)号：US20140209851A1

公开(公告)日：2014-07-31

申请号：US14243710

申请日：2014-04-02

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Jian Li

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L21/06 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1675

Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

Abstract translation: 一些实施例包括用于制造存储器单元结构的方法。 存储单元可以形成为具有可编程材料，以直接抵抗具有与可编程材料不同的膨胀系数的材料。 可以在可编程材料附近形成保持壳。 可以对存储单元进行热处理以将存储单元的温度升高至至少约300℃，从而在存储单元内引起热诱导的应力。 保持壳可以提供基本上平衡热诱导应力的应力。 一些实施例包括存储器单元结构。 这些结构可以包括直接针对氮化硅的可编程材料，其具有小于或等于约200兆帕的内部应力。 该结构还可以包括具有至少约500兆帕的内应力的保持壳氮化硅。

公开(公告)号：US08728932B2

公开(公告)日：2014-05-20

申请号：US13734476

申请日：2013-01-04

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: H01L21/4763

CPC classification number: H01L45/06 ,  H01L21/76885 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures.

Abstract translation: 具有由电介质台面的侧壁支撑的导电层的存储器单元和集成电路的触点，以及包含这种触点的存储单元以及形成这种结构的方法。

公开(公告)号：US20130292628A1

公开(公告)日：2013-11-07

申请号：US13903307

申请日：2013-05-28

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: H01L45/00

CPC classification number: H01L45/145 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1683

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.

Abstract translation: 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。 形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成亚化学计量氧化物，在亚化学计量氧化物上形成第二导电元件，以及通过使亚化学计量氧化物氧化成氧化环境来氧化亚化学计量氧化物的边缘 以限定氧化物中心附近的受控氧空位传导路径。

公开(公告)号：US20130286727A1

公开(公告)日：2013-10-31

申请号：US13926397

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Gurtej S. Sandhu

IPC: G11C11/16 ,  H01L43/02

CPC classification number: G11C11/16 ,  G11C11/161 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08

Abstract: Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise an annular STT stack including a nonmagnetic material between a first ferromagnetic material and a second ferromagnetic material and a soft magnetic material surrounding at least a portion of the annular STT stack.

Abstract translation: 本文描述了旋转转矩传递（STT）存储单元结构和方法。 一个或多个STT存储器单元结构包括在第一铁磁材料和第二铁磁材料之间包括非磁性材料的环形STT堆叠和围绕环形STT堆叠的至少一部分的软磁材料。

公开(公告)号：US20130265822A1

公开(公告)日：2013-10-10

申请号：US13906964

申请日：2013-05-31

Applicant: Micron Technology, Inc.

Inventor： Jun Liu

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0009 ,  G11C11/5614 ,  G11C13/0011 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/24 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

Abstract: Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

Abstract translation: 一些实施例包括具有具有第一电极，第二电极和位于第一和第二电极之间的电介质的存储单元的装置和方法。 电介质可以被配置为允许存储单元在电介质中形成来自第一电极的材料的一部分的导电路径，以表示存储在存储单元中的信息的第一值。 电介质还可以被配置为允许存储器单元破坏导电路径以表示存储在存储单元中的信息的第二值。

公开(公告)号：US20130248810A1

公开(公告)日：2013-09-26

申请号：US13889777

申请日：2013-05-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Mike Violette ,  Jon Daley

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

Abstract: A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.

Abstract translation: 记忆元件及其形成方法。 存储元件包括支撑第一电极的基板，在第一电极上的电介质层，具有暴露第一电极的一部分的通孔，形成在通孔的侧壁上并与第一电极的暴露部分接触的相变材料层， 形成在相变材料层上的绝缘材料和形成在绝缘材料上并与相变材料层接触的第二电极。

公开(公告)号：US20130215668A1

公开(公告)日：2013-08-22

申请号：US13847205

申请日：2013-03-19

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Wenzhou Chen

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/009 ,  G11C2013/0092

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract translation: 本文描述了与多电平相变存储器单元相关联的方法，装置和系统。 本公开的一个或多个实施例包括通过将相变存储器单元置于复位状态来操作相变存储器件，并将所选择的编程脉冲施加到相变存储器单元，以将该单元编程为多个 在复位状态和与单元相关联的设置状态之间的中间状态。 所选择的编程脉冲包括在特定持续时间内施加的最高幅度，该特定持续时间取决于存储器单元将被编程的中间状态数目中的哪一个。