公开(公告)号：US20180061471A1

公开(公告)日：2018-03-01

申请号：US15679032

申请日：2017-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher J. Kawamura ,  Scott J. Derner

IPC: G11C11/22 ,  G11C11/4091 ,  H01L27/11504

CPC classification number: G11C11/2275 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2293 ,  G11C11/2297 ,  G11C11/4091 ,  G11C11/5657 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11509

Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage of a first cell plate of a capacitor to change the voltage of a second cell plate of the capacitor, a second digit line, and a second sense node. The voltage of the second cell plate and the second digit line is decreased to change the voltage of the first cell plate, a first digit line, and a first sense node. The first node is driven to a first voltage and the second node is driven to a second voltage responsive to the voltage of the first node being greater than the second node. The first node is driven to the second voltage and the second node is driven to the first voltage responsive to the voltage of the first node being less than the second node.

公开(公告)号：US09715919B1

公开(公告)日：2017-07-25

申请号：US15188890

申请日：2016-06-21

Applicant: Micron Technology, Inc.

Inventor： Charles L. Ingalls ,  Scott J. Derner

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2275

Abstract: Methods, systems, and apparatuses for memory array bit inversion are described. A memory cell (e.g., a ferroelectric memory cell) may be written with a charge associated with a logic state that may be the inverse of the intended logic state of the cell. That is, the actual logic state of one or more memory cells may be inverted, but the intended logic state of the memory cells may remain unchanged. Different sets of transistors may be configured around a sense component of a cell to enable reading and writing of intended and inverted logic states from or to the cell. For instance, a first set of transistors may be used to read the logic state currently stored at a memory cell, while a second set of transistors may be used to read a logic state inverted from the currently stored logic state.

公开(公告)号：US09076501B2

公开(公告)日：2015-07-07

申请号：US13970518

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Zhong-yi Xia ,  Scott J. Derner ,  Charles L. Ingalls ,  Howard C. Kirsch

IPC: G11C16/28 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4091 ,  G11C16/28

Abstract: Apparatuses, sense amplifier circuits, and methods for operating a sense amplifier circuit in a memory are described. An example apparatus includes a sense amplifier circuit configured to be coupled to a digit line and configured to, during a memory access operation, drive the digit line to a voltage that indicates the logical value of the charge stored by a memory cell coupled to the digit line. During an initial time period of the memory access operation, the sense amplifier circuit is configured to drive the digit line to a first voltage that indicates the logical value of the charge stored by the memory cell. After the initial time period, the sense amplifier circuit is configured to drive the digit line to a second voltage different than the first voltage that indicates the logical value of the charge stored by the memory cell.

Abstract translation: 描述了用于在存储器中操作读出放大器电路的装置，读出放大器电路和方法。 示例性装置包括读出放大器电路，其被配置为耦合到数字线并且被配置为在存储器访问操作期间将数字线驱动到指示由耦合到数字的存储器单元存储的电荷的逻辑值的电压 线。 在存储器访问操作的初始时间周期期间，读出放大器电路被配置为将数字线驱动到指示由存储器单元存储的电荷的逻辑值的第一电压。 在初始时间段之后，读出放大器电路被配置为将数字线驱动到不同于指示由存储器单元存储的电荷的逻辑值的第一电压的第二电压。

公开(公告)号：US09070425B2

公开(公告)日：2015-06-30

申请号：US14068940

申请日：2013-10-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls ,  Howard Kirsch ,  Tae H. Kim

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/12

CPC classification number: G11C7/08 ,  G11C7/12

Abstract: Some embodiments include apparatuses and methods having a first data line, a second data line, a first transistor, a sense amplifier, and a circuit. The first transistor can operate to couple the first data line to a first node during a first stage of an operation of obtaining information from a memory cell associated with the first data line. The second transistor can operate to couple the second data line to a second node during the first stage. The circuit can operate to apply a first signal to a gate of the first transistor during the operation and to apply a second signal to a gate of the second transistor during the operation. The sense amplifier can operate to perform a sense function on the first and second data lines during a second stage of the operation. Additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有第一数据线，第二数据线，第一晶体管，读出放大器和电路的装置和方法。 在从与第一数据线相关联的存储器单元获得信息的操作的第一阶段期间，第一晶体管可以操作以将第一数据线耦合到第一节点。 第二晶体管可以在第一阶段期间将第二数据线耦合到第二节点。 电路可操作以在操作期间将第一信号施加到第一晶体管的栅极，并且在操作期间将第二信号施加到第二晶体管的栅极。 感测放大器可以在操作的第二阶段期间操作以在第一和第二数据线上执行感测功能。 描述附加的装置和方法。

公开(公告)号：US11705186B2

公开(公告)日：2023-07-18

申请号：US17497382

申请日：2021-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G11C7/06 ,  G11C8/08 ,  G11C11/4099 ,  G11C7/14

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4094 ,  G11C7/14 ,  G11C11/4099

Abstract: An example apparatus includes a sense amplifier, a plurality of storage memory cells coupled to the sense amplifier via a first digit line, and a plurality of offset memory cells coupled to the sense amplifier via a second digit line. The plurality of storage memory cells and the plurality of offset memory cells can comprise an array of memory cells. Each of the storage memory cells and the offset memory cells can include a respective capacitor having a particular capacitance.

公开(公告)号：US20220384448A1

公开(公告)日：2022-12-01

申请号：US17876461

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Jiyun Li ,  Scott J. Derner

IPC: H01L27/108 ,  H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4074

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

公开(公告)号：US11437381B2

公开(公告)日：2022-09-06

申请号：US16785942

申请日：2020-02-10

Applicant: Micron Technology, inc.

Inventor： Jiyun Li ,  Scott J. Derner

IPC: H01L27/108 ,  H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4074

Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.

公开(公告)号：US11380388B2

公开(公告)日：2022-07-05

申请号：US17140540

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: G11C11/24 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/4091 ,  H01L27/12 ,  H01L29/786 ,  H01L27/11507 ,  H01L27/11509

Abstract: In the examples disclosed herein, a memory array can have a first group of memory cells coupled to a first digit line at a first level and a second group of memory cells coupled to a second digit line at the first level. A third digit line can be at a second level and can be coupled to a main sense amplifier. A first vertical thin film transistor (TFT) can be at a third level between the first and second levels can be coupled between the first digit line and the third digit line. A second vertical TFT can be at the third level and can be coupled between the second digit line and the third digit line. A local sense amplifier can be coupled to the first and second digit lines.

公开(公告)号：US20220157836A1

公开(公告)日：2022-05-19

申请号：US17589573

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Charles L. Ingalls

IPC: H01L27/11507 ,  H01L29/78 ,  H01L27/11514 ,  H01L23/528 ,  H01L27/108 ,  H01L29/08

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

公开(公告)号：US20220131003A1

公开(公告)日：2022-04-28

申请号：US17568133

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Steve V. Cole ,  Scott J. Derner ,  Toby D. Robbs

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11587 ,  G11C11/22 ,  G11C11/4091

Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.