公开(公告)号：US20150229859A1

公开(公告)日：2015-08-13

申请号：US14616546

申请日：2015-02-06

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Jay Endsley ,  John Ladd ,  Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/374

CPC classification number: H04N5/374 ,  H01L27/14643 ,  H04N5/3577 ,  H04N5/365 ,  H04N5/3765 ,  H04N5/378

Abstract: A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.

Abstract translation: 生成控制脉冲，该第一控制信号线耦合到像素的传输门，以使得能够累积在该像素的光敏元件内的光电荷被传送到浮动扩散节点，该第一控制信号线具有与浮置的电容耦合 扩散节点。 在像素阵列的还具有与浮动扩散节点的电容耦合的第二信号线上产生馈通补偿脉冲。 馈通补偿脉冲以与控制脉冲的脉冲极性相反的脉冲极性产生，并被定时以与控制脉冲一致，使得控制脉冲到浮动扩散节点的电容馈通减小。

公开(公告)号：US20150201142A1

公开(公告)日：2015-07-16

申请号：US14638161

申请日：2015-03-04

Applicant: Rambus Inc.

Inventor： Craig M. Smith ,  Michael Guidash ,  Jay Endsley ,  Thomas Vogelsang ,  James E. Harris

IPC: H04N5/378

CPC classification number: H04N5/3559 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H04N5/347 ,  H04N5/355 ,  H04N5/3741 ,  H04N5/37455 ,  H04N5/378

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

Abstract translation: 在集成电路图像传感器内的像素阵列中，评估多个像素中的每一个以确定响应于入射光在像素内积分的电荷是否超过第一阈值。 产生与集成在多个像素的至少一个子集中的电荷相对应的N位数字样本，然后将其应用于查找表以检索相应的M位数字值（M小于N），其中步长范围 由M位数字值的可能状态表示的电荷积分电平从基于第一阈值确定的起始电荷积分电平向上延伸。

公开(公告)号：US09036065B1

公开(公告)日：2015-05-19

申请号：US13864427

申请日：2013-04-17

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: H04N5/335 ,  H04N3/14 ,  H01L27/00 ,  H04N5/353 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H04N5/3535 ,  H04N5/355 ,  H04N5/35536 ,  H04N5/3745 ,  H04N5/378

Abstract: During an exposure interval within an integrated-circuit image sensor, a first sequence of sample values, obtained by iteratively sampling a first pixel, is accumulated within a counter. The counter is reset to clear the first count value, and then a second sequence of sample values, obtained by iteratively sampling a second pixel, is accumulated within the counter.

Abstract translation: 在集成电路图像传感器中的曝光间隔期间，通过对第一像素进行迭代采样获得的第一采样值序列被累积在计数器内。 计数器被复位以清除第一计数值，然后在计数器内累积通过迭代采样第二像素获得的第二采样值序列。

公开(公告)号：US20130132685A1

公开(公告)日：2013-05-23

申请号：US13653033

申请日：2012-10-16

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Brent Haukness ,  Stephen Charles Bowyer

IPC: G06F12/00

CPC classification number: G11C11/4096 ,  G06F12/00 ,  G06F13/1694 ,  G11C11/4087 ,  G11C11/4091

Abstract: Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.

Abstract translation: 实施例通常涉及用于存储器设备和存储器控制器之间的通信的命令协议和/或相关电路和装置。 在一个实施例中，存储器控制器包括用于向存储器件发送命令的接口，其中存储器件包括位线复用器，并且通过包括字线选择的命令协议序列执行存储器设备内的存储器单元的访问， 通过位线多路复用器的位线选择。 在另一个实施例中，存储器件包括位线多路复用器，并且还包括接口，用于接收指定字线选择的命令协议序列，随后由位线复用器进行位线选择。

公开(公告)号：US20240345735A1

公开(公告)日：2024-10-17

申请号：US18681716

申请日：2022-08-08

Applicant: Rambus Inc.

Inventor： Brent Steven Haukness ,  Christopher Haywood ,  Torsten Partsch ,  Thomas Vogelsang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes memory core circuitry including an array of DRAM storage cells organized into bank groups. Each bank group includes multiple banks, where each of the multiple banks includes addressable columns of DRAM storage cells. The DRAM device includes signal interface circuitry having dedicated write data path circuitry and dedicated read data path circuitry. Selector circuitry, for a first memory transaction, selectively couples at least one of the addressable columns of DRAM storage cells to the dedicated read data path circuitry or the dedicated write data path circuitry.

公开(公告)号：US20240302977A1

公开(公告)日：2024-09-12

申请号：US18607906

申请日：2024-03-18

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Liji Gopalakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0673

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

公开(公告)号：US12072807B2

公开(公告)日：2024-08-27

申请号：US17058492

申请日：2019-05-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/00 ,  G06F12/0864

CPC classification number: G06F12/0864 ,  G06F2212/6032

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US12026104B2

公开(公告)日：2024-07-02

申请号：US17438844

申请日：2020-03-19

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Craig E. Hampel

IPC: G06F13/16 ,  G06F7/483

CPC classification number: G06F13/1605 ,  G06F7/483

Abstract: Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

公开(公告)号：US20240177794A1

公开(公告)日：2024-05-30

申请号：US18367381

申请日：2023-09-12

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C29/52 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C29/52 ,  G11C11/4087 ,  G11C11/4093

Abstract: Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.

公开(公告)号：US20240127903A1

公开(公告)日：2024-04-18

申请号：US18474643

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Torsten Partsch

IPC: G11C29/52 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C29/52 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.