公开(公告)号：US10529620B2

公开(公告)日：2020-01-07

申请号：US15830838

申请日：2017-12-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Senaka Krishna Kanakamedala ,  Fumitaka Amano ,  Genta Mizuno

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524 ,  H01L21/28 ,  H01L21/285

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

公开(公告)号：US20200006375A1

公开(公告)日：2020-01-02

申请号：US16020505

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Yingda Dong ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail. Each memory stack structure includes a vertical semiconductor channel, a blocking dielectric contacting an outer sidewall of the vertical semiconductor channel, and a charge storage layer contacting an outer sidewall of the blocking dielectric, vertically extending continuously through each level of the electrically conductive strips, and having a vertically undulating lateral thickness.

公开(公告)号：US10453854B2

公开(公告)日：2019-10-22

申请号：US15813625

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshihiro Kanno ,  Senaka Krishna Kanakamedala ,  Raghuveer S. Makala ,  Yanli Zhang ,  Jin Liu ,  Murshed Chowdhury

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20190229125A1

公开(公告)日：2019-07-25

申请号：US15877219

申请日：2018-01-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Hiroyuki Kinoshita ,  Yanli Zhang ,  James Kai ,  Johann Alsmeier ,  Stephen Ross ,  Senaka Kanakamedala

IPC: H01L27/11556 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: A three-dimensional memory device includes semiconductor devices located on a semiconductor substrate, lower interconnect level dielectric layers embedding lower interconnect structures, an alternating stack of insulating layers and electrically conductive layers overlying the lower interconnect level dielectric layers and including stepped surfaces, memory stack structures vertically extending through the alternating stack, and contact via structures extending downward from the stepped surfaces through underlying portions of the alternating stack to the lower interconnect structures. Each of the contact via structures laterally contacts an electrically conductive layer located at the stepped surfaces, and provides electrical interconnection to an underlying semiconductor device. A top portion of each contact via structures contacts an electrically conductive layer, and is electrically isolated from other underlying electrically conductive layers.

公开(公告)号：US10355139B2

公开(公告)日：2019-07-16

申请号：US15291640

申请日：2016-10-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Keerti Shukla ,  Fei Zhou ,  Somesh Peri

IPC: H01L29/788 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11573

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.

公开(公告)号：US10355012B2

公开(公告)日：2019-07-16

申请号：US15632983

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seiji Shimabukuro ,  Raghuveer S. Makala

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. A retro-stepped dielectric material portion comprising a compressive-stress-generating dielectric material on stepped surfaces of the alternating stack. Memory stack structures are formed through the first-tier alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a memory film. A patterned tensile-stress-generating material layer is formed over the retro-stepped dielectric material portion in a region that is laterally spaced outward from an outer periphery of a topmost layer within the alternating stack. The patterned tensile-stress-generating material layer applies a tensile stress to the retro-stepped dielectric material portion and to the alternating stack to compensate for the compressive stress generated by the retro-stepped dielectric material portion.

公开(公告)号：US10290652B1

公开(公告)日：2019-05-14

申请号：US15992603

申请日：2018-05-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/285 ,  H01L21/768 ,  H01L23/535

Abstract: A method of forming a three-dimensional memory device includes providing an alternating stack of insulating layers and sacrificial material layers located between a first trench and a second trench, forming memory stack structures extending vertically through the alternating stack, wherein each of the memory stack structures contains a memory film and a vertical semiconductor channel, removing the sacrificial material layers selective to the insulating layers through the first and the second trenches to form backside recesses having a first proximal region adjacent to the first trench, a second proximal region adjacent to the second trench and a distal region located between the first and the second proximal regions, and forming fluorine-free tungsten layers in the respective backside recesses such that each fluorine-free tungsten layer has a greater thickness in the distal region than in the first and the second proximal regions.

公开(公告)号：US10262945B2

公开(公告)日：2019-04-16

申请号：US15581575

申请日：2017-04-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Murshed Chowdhury ,  Keerti Shukla ,  Tomohisa Abe ,  Yao-Sheng Lee ,  James Kai

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/115 ,  H01L49/02 ,  H01L23/522 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/167 ,  H01L23/532

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.

公开(公告)号：US20180175054A1

公开(公告)日：2018-06-21

申请号：US15891574

申请日：2018-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Raghuveer S. Makala ,  Ching-Huang Lu ,  Yao-Sheng Lee ,  Jian Chen

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/11565 ,  H01L29/40117 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

公开(公告)号：US20180151588A1

公开(公告)日：2018-05-31

申请号：US15361842

申请日：2016-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Kengo Kajiwara ,  Raghuveer S. Makala

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.