公开(公告)号：US08841165B2

公开(公告)日：2014-09-23

申请号：US14010574

申请日：2013-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei Noda

IPC: H01L21/00 ,  H01L27/115 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L27/1156 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes an oxide semiconductor film including a pair of first regions, a pair of second regions, and a third region; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode provided between the pair of electrodes with the gate insulating film interposed therebetween. The pair of first regions overlap with the pair of electrodes, the third region overlaps with the gate electrode, and the pair of second regions are formed between the pair of first regions and the third region. The pair of second regions and the third region each contain nitrogen, phosphorus, or arsenic. The pair of second regions have a higher element concentration than the third region.

Abstract translation: 半导体器件包括包括一对第一区域，一对第二区域和第三区域的氧化物半导体膜; 与氧化物半导体膜接触的一对电极; 氧化物半导体膜上的栅极绝缘膜; 以及设置在所述一对电极之间的栅电极，其间插入有所述栅极绝缘膜。 所述一对第一区域与所述一对电极重叠，所述第三区域与所述栅电极重叠，并且所述一对第二区域形成在所述一对第一区域与所述第三区域之间。 一对第二区域和第三区域各自含有氮，磷或砷。 一对第二区域具有比第三区域更高的元件浓度。

公开(公告)号：US20250120179A1

公开(公告)日：2025-04-10

申请号：US18983443

申请日：2024-12-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H10D86/60 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H10D30/67 ,  H10D62/80 ,  H10D64/68 ,  H10D86/40

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

公开(公告)号：US12199104B2

公开(公告)日：2025-01-14

申请号：US17206906

申请日：2021-03-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Atsushi Hirose ,  Masashi Tsubuku ,  Kosei Noda

IPC: H01L27/12 ,  H01L21/8234 ,  H01L27/15 ,  H01L29/24 ,  H01L29/36 ,  H01L29/786 ,  H01L33/00 ,  H01L33/02 ,  H04M1/02 ,  H04R1/02 ,  H10K59/35

Abstract: An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

公开(公告)号：US11837461B2

公开(公告)日：2023-12-05

申请号：US17010151

申请日：2020-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kei Takahashi ,  Kouhei Toyotaka ,  Masashi Tsubuku ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/26 ,  G06K19/077 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088 ,  H01L29/24 ,  H01L29/66 ,  G11C7/00 ,  G11C19/28 ,  H02M3/07

CPC classification number: H01L29/78609 ,  G06K19/07758 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  G11C7/00 ,  G11C19/28 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US11742432B2

公开(公告)日：2023-08-29

申请号：US17565771

申请日：2021-12-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Masashi Tsubuku ,  Kosei Noda

IPC: H01L33/00 ,  H01L29/786 ,  H01L27/12 ,  H01L27/02 ,  H01L21/66

CPC classification number: H01L29/7869 ,  H01L27/0207 ,  H01L27/1225 ,  H01L29/78696 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

公开(公告)号：US11728350B2

公开(公告)日：2023-08-15

申请号：US17672901

申请日：2022-02-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L27/00 ,  H01L29/00 ,  G02F1/1333 ,  H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24

CPC classification number: H01L27/1225 ,  G02F1/1337 ,  G02F1/1368 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/136277 ,  H01L27/124 ,  H01L27/1214 ,  H01L27/1248 ,  H01L29/24 ,  H01L29/517 ,  H01L29/7869 ,  H01L29/78609

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

公开(公告)号：US11631756B2

公开(公告)日：2023-04-18

申请号：US17073520

申请日：2020-10-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta Endo ,  Toshinari Sasaki ,  Kosei Noda

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/786 ,  H01L29/423 ,  H01L21/425 ,  H01L21/02 ,  H01L21/477 ,  H01L21/28

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

公开(公告)号：US20220181359A1

公开(公告)日：2022-06-09

申请号：US17672901

申请日：2022-02-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroki Ohara ,  Toshinari Sasaki ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. Au oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

公开(公告)号：US11152493B2

公开(公告)日：2021-10-19

申请号：US14540184

申请日：2014-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Kosei Noda ,  Hiroki Ohara ,  Toshinari Sasaki ,  Junichiro Sakata

IPC: H01L21/00 ,  H01L21/477 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12

Abstract: A highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics, and a manufacturing method thereof. In the manufacturing method of the semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region is an oxide semiconductor layer, heat treatment which reduces impurities such as moisture to improve the purity of the oxide semiconductor layer and oxidize the oxide semiconductor layer (heat treatment for dehydration or dehydrogenation) is performed. Not only impurities such as moisture in the oxide semiconductor layer but also those existing in a gate insulating layer are reduced, and impurities such as moisture existing in interfaces between the oxide semiconductor layer and films provided over and under and in contact with the oxide semiconductor layer are reduced.

公开(公告)号：US11004983B2

公开(公告)日：2021-05-11

申请号：US16778336

申请日：2020-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Kosei Noda ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Hikaru Harada

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/11 ,  H01L49/02 ,  H01L27/12 ,  G06F15/76 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.