公开(公告)号：US20080242022A1

公开(公告)日：2008-10-02

申请号：US11693829

申请日：2007-03-30

申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Gowrishankar Chindalore ,  David Sing ,  Jane Yater

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs.

摘要翻译： 电子设备可以包括在电介质层内具有DSE的非易失性存储单元。 一方面，形成电子器件的方法可以包括将第一电荷存储材料植入和成核以形成DSE。 该过程还可以包括植入第二电荷储存材料并生长DSE，使得DSE包括第一和第二电荷存储材料。 在另一方面，形成电子器件的工艺可以包括在电介质层上形成半导体层，注入电荷存储材料，以及退火介电层。 在退火之后，基本上没有一种电荷存储材料保留在电介质层内的裸露区域内。 在第三方面，在介电层内，第一组DSE可以与第二组DSE间隔开，其中基本上没有DSE位于第一组DSE和第二组DSE之间。

公开(公告)号：US20080227254A1

公开(公告)日：2008-09-18

申请号：US11685297

申请日：2007-03-13

申请人： Rajesh A. Rao ,  Ramachandran Muralidhar

发明人： Rajesh A. Rao ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.

摘要翻译： 包括非易失性存储单元的电子设备可以包括包括第一部分和第二部分的基板，其中第一部分内的第一主表面位于比第二部分内的第二主表面低的高度处。 电子设备还可以包括覆盖第一部分的电荷存储堆叠，其中电荷存储堆叠包括不连续的存储元件。 电子器件还可以包括覆盖第一部分的控制栅电极和覆盖第二部分的选择栅电极，其中选择栅电极包括侧壁间隔物。 在特定实施例中，可以使用一种工艺来形成电荷存储堆和控制栅电极。 在形成电荷存储堆和控制栅电极之后可以形成半导体层，以在不同的高度实现具有不同主表面的衬底。 选择栅电极可以形成在半导体层上。

公开(公告)号：US20080182375A1

公开(公告)日：2008-07-31

申请号：US11669307

申请日：2007-01-31

申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

IPC分类号： H01L21/336

CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7887

摘要： A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

摘要翻译： 在衬底上形成多位分离栅极存储器件。 在衬底上形成存储层。 在存储层上形成第一导电层。 去除导电层的一部分的厚度以留下导电层的柱和导电层的厚度减小的面积。 形成邻近柱的第一侧壁间隔物以覆盖导电层厚度减小区域的第一部分和第二部分。 柱子被一个选择门取代。 选择性地去除厚度减小的区域以留下第一和第二部分作为控制门。

公开(公告)号：US20080164512A1

公开(公告)日：2008-07-10

申请号：US11620075

申请日：2007-01-05

申请人： Rajesh A. Rao ,  Leo Mathew ,  Ramachandran Muralidhar ,  Bruce E. White

发明人： Rajesh A. Rao ,  Leo Mathew ,  Ramachandran Muralidhar ,  Bruce E. White

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  H01L21/84 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/1203 ,  H01L27/15 ,  H01L29/66825 ,  H01L29/788

摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

摘要翻译： 半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。 互连层在半导体层之上。 存储器阵列位于顶部半导体层部分和互连层的一部分中。 通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。 结果是存储器阵列从背面接收光并被擦除。

公开(公告)号：US20080105945A1

公开(公告)日：2008-05-08

申请号：US11964309

申请日：2007-12-26

申请人： Robert Steimle ,  Ramachandran Muralidhar ,  Bruce White

发明人： Robert Steimle ,  Ramachandran Muralidhar ,  Bruce White

IPC分类号： H01L27/07

CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11573

摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.

摘要翻译： 集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。 集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。 集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。 当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。 在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。

公开(公告)号：US07352631B2

公开(公告)日：2008-04-01

申请号：US11061005

申请日：2005-02-18

申请人： James D. Burnett ,  Ramachandran Muralidhar

发明人： James D. Burnett ,  Ramachandran Muralidhar

IPC分类号： G11C11/34

CPC分类号： H01L21/26586 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/1083 ,  H01L29/7881

摘要： A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The active hole removal is faster than passively allowing holes to be removed, which can take milliseconds. The active hole removal can be achieved by reducing the drain voltage to a negative voltage and reducing the gate voltage as well. This results in directly withdrawing the holes from the floating body to the drain. Alternatively, reducing the drain voltage while maintaining current flow stops impact ionization while sub channel current collects the holes. Further alternatively, applying a negative gate voltage causes electrons generated by band to band tunneling and impact ionization near the drain to recombine with holes.

摘要翻译： 一种用于加速具有浮体的非易失性存储装置的编程的技术主动地从执行热载流子注入（HCI）之后累积的浮体中去除空穴。 HCI和有源孔去除的步骤可以交替，直到编程完成。 有源孔移除比被动地更快地允许孔被去除，这可能需要几毫秒。 有源孔去除可以通过将漏极电压降低到负电压并降低栅极电压来实现。 这导致从浮体直接排出孔到排水管。 或者，在保持电流的同时降低漏极电压停止冲击电离，而子通道电流收集孔。 或者，施加负栅极电压使得通过带状隧穿产生的电子和靠近漏极的冲击电离与空穴重新组合。

公开(公告)号：US20070082495A1

公开(公告)日：2007-04-12

申请号：US11244516

申请日：2005-10-06

申请人： Leo Mathew ,  Rajesh Rao ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Rajesh Rao ,  Ramachandran Muralidhar

IPC分类号： H01L29/76 ,  H01L21/461 ,  H01L21/302 ,  H01L29/745

CPC分类号： H01L29/42368 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/32139 ,  H01L28/91 ,  H01L29/512 ,  H01L29/513

摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.

摘要翻译： 半导体器件包括由导电材料形成的多个支柱。 通过使用多个纳米晶体作为用于图案化导电材料的硬掩模来形成柱。 导电材料的厚度决定了支柱的高度。 同样，柱的宽度由纳米晶体的直径决定。 在一个实施例中，柱由多晶硅形成，并且用作具有良好电荷保持和低电压操作的非易失性存储单元的电荷存储区。 在另一个实施例中，支柱由金属形成，并且用作具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器的平板电极，而不增加集成电路的表面积。

公开(公告)号：US07195983B2

公开(公告)日：2007-03-27

申请号：US10930892

申请日：2004-08-31

申请人： Gowrishankar L. Chindalore ,  James David Burnett ,  Craig T. Swift ,  Ramachandran Muralidhar

发明人： Gowrishankar L. Chindalore ,  James David Burnett ,  Craig T. Swift ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66833 ,  H01L29/7881

摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.

摘要翻译： 非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。 作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。 这导致通过冲击电离产生电子/空穴对更困难。 因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。 具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。

公开(公告)号：US20060220102A1

公开(公告)日：2006-10-05

申请号：US11083878

申请日：2005-03-18

申请人： Leo Mathew ,  Ramachandran Muralidhar ,  Tab Stephens

发明人： Leo Mathew ,  Ramachandran Muralidhar ,  Tab Stephens

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.

摘要翻译： 非易失性存储单元可以包括衬底，覆盖衬底的有源区和覆盖衬底的电容器结构。 从平面图，电容器结构围绕有源区域。 在一个实施例中，非易失性存储单元包括浮置栅电极和控制栅电极。 电容器结构包括第一电容器部分，第一电容器部分包括第一电容器电极和第二电容器电极。 第一电容器电极电连接到浮置栅电极，并且第二电容器电极电连接到控制栅电极。 用于形成非易失性存储单元的方法可以包括在衬底上形成有源区，并在衬底上形成电容器结构，其中从平面图看，电容器结构围绕有源区。

公开(公告)号：US20060186456A1

公开(公告)日：2006-08-24

申请号：US11060996

申请日：2005-02-18

申请人： James Burnett ,  Ramachandran Muralidhar

发明人： James Burnett ,  Ramachandran Muralidhar

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/1083 ,  H01L29/7881

摘要： A non-volatile memory (NVM) device formed in a semiconductor-on-insulator (SOI) substrate has a trap region on the source side only to speed up the process of programming. During programming of an NVM device in partially depleted SOI, holes are generated that slow down the formation of electrons hot enough to jump to the storage layer of the NVM. To reduce this effect, the trap region is formed below the lightly-doped portion of the source region and preferably extends to an area under the gate on the source side. This can be achieved using an angled implant of a neutral impurity, such as xenon, argon, or germanium, while masking the drain side. The trap region thus extends under the gate on the source side to recombine with holes that are generated during programming. The trap region also extends to contact the source.

摘要翻译： 形成在绝缘体上半导体（SOI））衬底中的非易失性存储器（NVM）器件在源极上具有陷阱区域，仅用于加速编程过程。 在部分耗尽的SOI中的NVM器件的编程期间，产生空穴，其减慢热到足以跳到NVM的存储层的电子的形成。 为了减小这种影响，陷波区域形成在源极区域的轻掺杂部分下方，优选地延伸到源极侧的栅极下方的区域。 这可以使用中性杂质（例如氙，氩或锗）的倾斜注入来实现，同时掩蔽漏极侧。 陷阱区域因此在源极侧的栅极下方与编程期间产生的孔重新组合。 陷阱区域也延伸以接触源。