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    Non-volatile memory cell including a capacitor structure and processes for forming the same
    1.
    发明申请
    Non-volatile memory cell including a capacitor structure and processes for forming the same 有权
    包括电容器结构的非易失性存储单元及其形成方法

    公开(公告)号：US20060220102A1

    公开(公告)日：2006-10-05

    申请号：US11083878

    申请日：2005-03-18

    申请人： Leo Mathew ,  Ramachandran Muralidhar ,  Tab Stephens

    发明人： Leo Mathew ,  Ramachandran Muralidhar ,  Tab Stephens

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

    摘要： A non-volatile memory cell can include a substrate, an active region overlying the substrate, and a capacitor structure overlying the substrate. From a plan view, the capacitor structure surrounds the active region. In one embodiment, the non-volatile memory cell includes a floating gate electrode and a control gate electrode. The capacitor structure comprises a first capacitor portion, and the first capacitor portion comprises a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is electrically connected to the floating gate electrode, and the second capacitor electrode is electrically connected to the control gate electrode. A process for forming the non-volatile memory cell can include forming an active region over a substrate, and forming a capacitor structure over the substrate, wherein from a plan view, the capacitor structure surrounds the active region.

    摘要翻译： 非易失性存储单元可以包括衬底，覆盖衬底的有源区和覆盖衬底的电容器结构。 从平面图，电容器结构围绕有源区域。 在一个实施例中，非易失性存储单元包括浮置栅电极和控制栅电极。 电容器结构包括第一电容器部分，第一电容器部分包括第一电容器电极和第二电容器电极。 第一电容器电极电连接到浮置栅电极，并且第二电容器电极电连接到控制栅电极。 用于形成非易失性存储单元的方法可以包括在衬底上形成有源区，并在衬底上形成电容器结构，其中从平面图看，电容器结构围绕有源区。

    Phase change memory cell with heater and method therefor
    2.
    发明授权
    Phase change memory cell with heater and method therefor 有权
    具有加热器的相变存储器单元及其方法

    公开(公告)号：US08043888B2

    公开(公告)日：2011-10-25

    申请号：US12016733

    申请日：2008-01-18

    申请人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

    摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

    摘要翻译： 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

    Transistor with independent gate structures
    3.
    发明授权
    Transistor with independent gate structures 有权
    具有独立门结构的晶体管

    公开(公告)号：US07192876B2

    公开(公告)日：2007-03-20

    申请号：US10443375

    申请日：2003-05-22

    申请人： Leo Mathew ,  Robert F. Steimle ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Robert F. Steimle ,  Ramachandran Muralidhar

    IPC分类号： H01L21/308

    CPC分类号： H01L29/785 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7881 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

    摘要： A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.

    摘要翻译： 制造具有独立栅极结构的晶体管的方法。 栅极结构各自与半导体结构的侧壁相邻。 该方法包括在包括沟道区域的半导体结构上沉积包括栅极材料层的至少一个共形层。 在晶片上形成平面层。 平面层在衬底上方的位置处具有在大致最小一个共形层的顶表面下方的顶表面。 蚀刻至少一个共形层以去除半导体结构上的栅极材料。

    Semiconductor fabrication process with asymmetrical conductive spacers
    5.
    发明申请
    Semiconductor fabrication process with asymmetrical conductive spacers 有权
    具有不对称导电间隔物的半导体制造工艺

    公开(公告)号：US20050124130A1

    公开(公告)日：2005-06-09

    申请号：US11036860

    申请日：2005-01-13

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

    CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7842 ,  Y10S257/90

    摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

    摘要翻译： 半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。 导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。 源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。 间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。 在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调整通道植入物的需要。

    Integrated circuit having multiple memory types and method of formation
    6.
    发明授权
    Integrated circuit having multiple memory types and method of formation 失效
    具有多种存储器类型和形成方法的集成电路

    公开(公告)号：US06831310B1

    公开(公告)日：2004-12-14

    申请号：US10705504

    申请日：2003-11-10

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L2980

    CPC分类号： H01L27/108 ,  B82Y10/00 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/785 ,  H01L29/7881

    摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

    摘要翻译： 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

    CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS
    7.
    发明申请
    CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS 有权
    双栅极晶体管半导体制造工艺的限制间隔

    公开(公告)号：US20050101069A1

    公开(公告)日：2005-05-12

    申请号：US10695163

    申请日：2003-10-28

    申请人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

    发明人： Leo Mathew ,  Rode Mora ,  Bich-Yen Nguyen ,  Tab Stephens ,  Anne Vandooren

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

    CPC分类号： H01L29/785 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/66818

    摘要： A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.

    摘要翻译： 半导体制造工艺包括形成覆盖衬底的硅片。 栅极电介质形成在鳍片的主面上。 在鳍片的至少两个面上形成栅电极。 然后选择性地形成电介质间隔物并且限制在栅电极的侧壁，从而使大部分初级鳍片面露出。 此后，在主翅片面上形成硅化物。 在一个实施例中，栅电极的形成包括在鳍片和衬底上沉积多晶硅，在多晶硅上沉积覆盖层，在覆盖层上图案化光刻胶，并通过覆盖层和多晶硅蚀刻图案化的光致抗蚀剂，其中蚀刻 产生小于封盖层的宽度的多晶硅宽度，以在与可以形成约束间隔物的多晶硅侧壁相邻的封盖层下产生空隙。

    Transistor having three electrically isolated electrodes and method of formation
    8.
    发明授权
    Transistor having three electrically isolated electrodes and method of formation 有权
    具有三个电隔离电极的晶体管和形成方法

    公开(公告)号：US07098502B2

    公开(公告)日：2006-08-29

    申请号：US10705317

    申请日：2003-11-10

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L27/108 ,  H01L27/12 ,  H01L21/00 ,  H01L21/336

    CPC分类号： H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

    摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

    摘要翻译： 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

    Transistor with vertical dielectric structure
    9.
    发明授权
    Transistor with vertical dielectric structure 有权
    具有垂直电介质结构的晶体管

    公开(公告)号：US07018876B2

    公开(公告)日：2006-03-28

    申请号：US10871772

    申请日：2004-06-18

    申请人： Leo Mathew ,  Ramachandran Muralidhar

    发明人： Leo Mathew ,  Ramachandran Muralidhar

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7887

    摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.

    摘要翻译： 一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。 半导体结构包括沟道区（731）和源极/漏极区（707,709）。 晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。 在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。 在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。