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公开(公告)号：US07352631B2
公开(公告)日：2008-04-01
申请号：US11061005
申请日：2005-02-18
IPC分类号： G11C11/34
CPC分类号： H01L21/26586 , H01L27/115 , H01L27/11521 , H01L29/1083 , H01L29/7881
摘要： A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The active hole removal is faster than passively allowing holes to be removed, which can take milliseconds. The active hole removal can be achieved by reducing the drain voltage to a negative voltage and reducing the gate voltage as well. This results in directly withdrawing the holes from the floating body to the drain. Alternatively, reducing the drain voltage while maintaining current flow stops impact ionization while sub channel current collects the holes. Further alternatively, applying a negative gate voltage causes electrons generated by band to band tunneling and impact ionization near the drain to recombine with holes.
摘要翻译： 一种用于加速具有浮体的非易失性存储装置的编程的技术主动地从执行热载流子注入（HCI）之后累积的浮体中去除空穴。 HCI和有源孔去除的步骤可以交替，直到编程完成。 有源孔移除比被动地更快地允许孔被去除，这可能需要几毫秒。 有源孔去除可以通过将漏极电压降低到负电压并降低栅极电压来实现。 这导致从浮体直接排出孔到排水管。 或者，在保持电流的同时降低漏极电压停止冲击电离，而子通道电流收集孔。 或者，施加负栅极电压使得通过带状隧穿产生的电子和靠近漏极的冲击电离与空穴重新组合。
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公开(公告)号：US20120181549A1
公开(公告)日：2012-07-19
申请号：US13009029
申请日：2011-01-19
IPC分类号： H01L29/161 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
摘要翻译： 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。
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3.发明授权Process of forming an electronic device including a layer of discontinuous storage elements 有权形成包括不连续存储元件层的电子器件的工艺公开(公告)号：US07932189B2
公开(公告)日：2011-04-26
申请号：US11627817
申请日：2007-01-26
申请人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
发明人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/11524 , H01L29/7887 , Y10S977/932 , Y10S977/943
摘要： An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.
摘要翻译： 电子设备可以包括不连续的存储元件层。 覆盖不连续存储元件的电介质层可以是基本上无氢的。 形成电子器件的工艺可以包括在不连续的存储元件上形成包括硅的层。 在一个实施方案中，该方法包括至少基本上氧化所有该层。 在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成层并至少基本上全部氧化。
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公开(公告)号：US20090085024A1
公开(公告)日：2009-04-02
申请号：US11864246
申请日：2007-09-28
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A phase change memory cell has a first electrode, a plurality of pillars, and a second electrode. The plurality of pillars are electrically coupled with the first electrode. Each of the pillars comprises a phase change material portion and a heater material portion. The second electrode is electrically coupled to each of the pillars. In some examples, the pillars have a width less than 20 nanometers.
摘要翻译： 相变存储单元具有第一电极，多个柱和第二电极。 多个柱与第一电极电耦合。 每个支柱包括相变材料部分和加热器材料部分。 第二电极电耦合到每个支柱。 在一些示例中，支柱具有小于20纳米的宽度。
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5.发明授权Method for retaining nanocluster size and electrical characteristics during processing 有权在加工过程中保留纳米簇粒径和电气特性的方法公开(公告)号：US07432158B1
公开(公告)日：2008-10-07
申请号：US11459843
申请日：2006-07-25
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/8238 , H01L21/36
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/1052 , H01L27/11526 , H01L27/11531 , H01L29/42332 , H01L29/7881 , Y10S977/774 , Y10S977/779 , Y10S977/78 , Y10S977/943
摘要： A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.
摘要翻译： 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 第一介电层形成在半导体层上。 在第一部分上形成第一多个纳米团簇，并且在第二部分上形成第二多个纳米团簇。 在第一多个和第二多个纳米团簇的每个纳米簇周围形成氮化氧化物层。 在第一多个纳米团簇的氮化氧化物层上进行远程等离子体氮化。 从第二部分去除纳米团簇。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。
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公开(公告)号：US20080199996A1
公开(公告)日：2008-08-21
申请号：US11676403
申请日：2007-02-19
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Matthew T. Herrick , Narayanan C. Ramani , Robert F. Steimle
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521
摘要： A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
摘要翻译： 一种方法形成分离栅极存储器件。 将衬底上的选择栅极材料层图案化以形成第一侧壁。 邻近第一侧壁形成牺牲隔离物。 纳米团簇形成在包括在牺牲间隔物上的衬底上。 在形成纳米团簇层之后去除牺牲隔离物，其中在牺牲隔离物上形成的纳米团簇被去除并且其它纳米团簇保留。 在除去牺牲间隔物之后，在衬底上形成一层控制栅极材料。 分离栅极存储器件的控制栅极由控制栅极材料层形成，其中控制栅极位于剩余的纳米簇上。
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7.发明申请Split-gate thin film storage NVM cell with reduced load-up/trap-up effects 有权分流栅薄膜存储NVM单元，具有降低的加载/陷阱效应公开(公告)号：US20080188052A1
公开(公告)日：2008-08-07
申请号：US11671809
申请日：2007-02-06
申请人： Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
发明人： Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
摘要翻译： 公开了一种半导体工艺和装置，用于通过在衬底（1）上的第一介电层（2）上形成选择栅极结构（3）来形成分裂栅极薄膜存储NVM器件（10）。 在具有嵌入的纳米晶体（15,16）的第二介电层（5）上形成控制栅极结构（6），使得所述控制栅极（6）与所述选择栅极结构（3）相邻，但是通过间隙（8 ）; 在形成在选择栅极结构和控制栅极结构之间的间隙（8）下面的衬底（1）中形成浮置掺杂区（4）; 以及在所述衬底中形成源/漏区（11,12）以限定包括所述浮置掺杂区（4）的沟道区。
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8.发明申请公开(公告)号：US20080182428A1
公开(公告)日：2008-07-31
申请号：US11627817
申请日：2007-01-26
申请人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
发明人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/11524 , H01L29/7887 , Y10S977/932 , Y10S977/943
摘要： An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.
摘要翻译： 电子设备可以包括不连续的存储元件层。 覆盖不连续存储元件的电介质层可以是基本上无氢的。 形成电子器件的过程可以包括在不连续的存储元件上形成包括硅的层。 在一个实施方案中，该方法包括至少基本上氧化所有该层。 在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成该层并至少基本上全部氧化。
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公开(公告)号：US20080182377A1
公开(公告)日：2008-07-31
申请号：US11668210
申请日：2007-01-29
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/513 , H01L29/66772 , H01L29/7887
摘要： In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.
摘要翻译： 在制造多位存储单元时，在半导体衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 一层栅极材料形成在第二绝缘层之上并图案化以留下栅极部分。 蚀刻第二绝缘层以切割栅极部分，并将第二绝缘层的一部分留在第一绝缘层和栅极部分之间。 在第一绝缘层上形成纳米晶体。 纳米晶体的第一部分在第二绝缘层部分的第一侧上的栅极部分下方，并且纳米晶体的第二部分在第二绝缘层部分的第二侧上的栅极部分下方。 纳米晶体的第一和第二部分分别用于存储第一和第二位的逻辑状态。
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公开(公告)号：US20080121966A1
公开(公告)日：2008-05-29
申请号：US11530053
申请日：2006-09-08
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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