公开(公告)号：US20060214172A1

公开(公告)日：2006-09-28

申请号：US11090386

申请日：2005-03-23

申请人： Sheng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/08 ,  B82Y20/00 ,  H01L33/18 ,  H01L33/24 ,  H01L33/34 ,  H01L33/502 ,  Y10S977/834

摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

摘要翻译： 提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。 该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。 纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

公开(公告)号：US20050207265A1

公开(公告)日：2005-09-22

申请号：US11130983

申请日：2005-05-16

申请人： Sheng Hsu ,  Tingkai Li ,  David Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Hsu ,  Tingkai Li ,  David Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L45/00 ,  G11C8/02

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US20050037520A1

公开(公告)日：2005-02-17

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David Evans ,  Sheng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David Evans ,  Sheng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

摘要翻译： 当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃 通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

公开(公告)号：US20080026494A1

公开(公告)日：2008-01-31

申请号：US11494181

申请日：2006-07-26

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Wei Gao ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Wei Gao ,  Tingkai Li

IPC分类号： H01L21/00

CPC分类号： H05B33/10

摘要： A method of fabricating an electroluminescent device includes preparing a wafer and a doped-silicon oxide precursor solution. The doped-silicon oxide precursor solution is spin coated onto the wafer to form a doped-silicon oxide thin film on the wafer, which is baked at progressively increasing temperatures. The wafer is then rapidly thermally annealed, further annealed in a wet oxygen ambient atmosphere. A transparent top electrode is deposited on the doped-silicon oxide thin film, which is patterned, etched, and annealed. The doped-silicon oxide thin film and the wafer undergo a final annealing step to enhance electroluminescent properties.

摘要翻译： 制造电致发光器件的方法包括制备晶片和掺杂的氧化硅前体溶液。 将掺杂的氧化硅前体溶液旋涂在晶片上以在晶片上形成掺杂的氧化硅薄膜，其在逐渐升高的温度下烘烤。 然后将晶片快速热退火，在湿氧环境气氛中进一步退火。 透明的顶部电极沉积在掺杂的氧化硅薄膜上，其被图案化，蚀刻和退火。 掺杂氧化硅薄膜和晶片进行最终退火步骤以增强电致发光性能。

公开(公告)号：US20070015329A1

公开(公告)日：2007-01-18

申请号：US11216398

申请日：2005-08-31

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

摘要翻译： 提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。 可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

公开(公告)号：US20070010037A1

公开(公告)日：2007-01-11

申请号：US11175797

申请日：2005-07-05

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L21/00

CPC分类号： H01L33/34 ,  B82Y20/00 ,  H01L33/0012

摘要： A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.

摘要翻译： 已经提供了超晶格纳米晶Si-SiO 2电致发光（EL）器件及其制造方法。 该方法包括：提供Si衬底; 形成覆盖Si衬底的初始SiO 2层; 形成覆盖初始SiO 2层的初始多晶硅层; 形成覆盖在初始多晶硅层上的SiO 2层; 重复多晶硅和SiO 2层形成，形成超晶格; 用稀土元素掺杂超晶格; 沉积覆盖掺杂超晶格的电极; 并且形成EL器件。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层和退火来形成多晶硅层。 或者，DC溅射工艺沉积每个非晶硅层，并且在形成超晶格之后，通过退火非晶硅层形成多晶硅。 可以通过热退火或通过使用DC溅射工艺的沉积来形成二氧化硅。

公开(公告)号：US20080090317A1

公开(公告)日：2008-04-17

申请号：US11998341

申请日：2007-11-29

申请人： Sheng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

发明人： Sheng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

IPC分类号： H01L33/00

CPC分类号： H01L33/08 ,  B82Y20/00 ,  H01L33/18 ,  H01L33/24 ,  H01L33/34 ,  H01L33/502 ,  Y10S977/834

摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

摘要翻译： 提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。 该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。 纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

公开(公告)号：US20080026590A1

公开(公告)日：2008-01-31

申请号：US11494141

申请日：2006-07-26

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Tingkai Li

IPC分类号： H01L21/31

CPC分类号： C23C18/1295 ,  C23C18/1208 ,  C23C18/1279 ,  C23C18/1283

摘要： A method of making a doped silicon oxide thin film using a doped silicon oxide precursor solution includes mixing a silicon source in an organic acid and adding 2-methoxyethyl ether to the silicon source and organic acid to from a preliminary precursor solution. The resultant solution is heated, stirred and filtered. A doping impurity is dissolved in 2-methoxyethanol to from a doped source solution, and the resultant solution mixed with the previously described resultant solution to from a doped silicon oxide precursor solution. A doped silicon oxide thin film if formed on a wafer by spin coating. The thin film and the wafer are baked at progressively increasing temperatures and the thin film and the wafer are annealed.

摘要翻译： 使用掺杂的氧化硅前体溶液制造掺杂的氧化硅薄膜的方法包括将有机酸中的硅源混合并向硅源和有机酸中加入2-甲氧基乙醚至初始前体溶液。 将所得溶液加热，搅拌并过滤。 将掺杂杂质从掺杂的源溶液中溶解在2-甲氧基乙醇中，并将所得溶液与先前所述的溶液混合从掺杂的氧化硅前体溶液中。 如果通过旋涂在晶片上形成掺杂的氧化硅薄膜。 在逐渐升高的温度下烘烤薄膜和晶片，并对薄膜和晶片进行退火。

公开(公告)号：US20070238203A1

公开(公告)日：2007-10-11

申请号：US11403022

申请日：2006-04-11

申请人： Wei-Wei Zhuang ,  David Evans ,  Tingkai Li ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  David Evans ,  Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  H01L21/31691 ,  H01L22/14

摘要： A method of monitoring synthesis of PCMO precursor solutions includes preparing a PCMO precursor solution and withdrawing samples of the precursor solution at intervals during a reaction phase of the PCMO precursor solution synthesis. The samples of the PCMO precursor solution are analyzed by UV spectroscopy to determine UV transmissivity of the samples of the PCMO precursor solution and the samples used to form PCMO thin films. Electrical characteristics of the PCMO thin films formed from the samples are determined to identify PCMO thin films having optimal electrical characteristics. The UV spectral characteristics of the PCMO precursor solutions are correlated with the PCMO thin films having optimal electrical characteristics. The UV spectral characteristics are used to monitor synthesis of future batches of the PCMO precursor solutions, which will result in PCMO thin films having optimal electrical characteristics.

摘要翻译： 监测PCMO前体溶液合成的方法包括制备PCMO前体溶液，并在PCMO前体溶液合成反应期间间隔取出前体溶液样品。 通过紫外光谱分析PCMO前体溶液的样品，以确定PCMO前体溶液和用于形成PCMO薄膜的样品的UV透射率。 确定由样品形成的PCMO薄膜的电特性以鉴定具有最佳电特性的PCMO薄膜。 PCMO前体溶液的UV光谱特性与具有最佳电学特性的PCMO薄膜相关。 UV光谱特性用于监测未来批次的PCMO前体溶液的合成，这将导致具有最佳电特性的PCMO薄膜。

公开(公告)号：US20060099724A1

公开(公告)日：2006-05-11

申请号：US11314222

申请日：2005-12-21

申请人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

发明人： Sheng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。