公开(公告)号：US11049765B2

公开(公告)日：2021-06-29

申请号：US16866360

申请日：2020-05-04

Applicant: United Microelectronics Corp.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

公开(公告)号：US10892348B2

公开(公告)日：2021-01-12

申请号：US16396788

申请日：2019-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Bin-Siang Tsai ,  Ting-An Chien ,  Yi-Liang Ye

IPC: H01L29/66 ,  H01L21/62 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

公开(公告)号：US20200343371A1

公开(公告)日：2020-10-29

申请号：US16396788

申请日：2019-04-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Hsuan Chang ,  Bin-Siang Tsai ,  Ting-An Chien ,  Yi-Liang Ye

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/308

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

公开(公告)号：US20200185629A1

公开(公告)日：2020-06-11

申请号：US16241997

申请日：2019-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chin-Chia Yang

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer; performing a treatment process to rough a top surface of the first metal interconnection; and forming a carbon nanotube (CNT) junction on the first metal interconnection. Preferably, the treatment process further includes forming protrusions on the top surface of the first metal interconnection, in which the protrusions and the first metal interconnection comprise same material.

公开(公告)号：US20190355618A1

公开(公告)日：2019-11-21

申请号：US16011615

申请日：2018-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

公开(公告)号：US20170365510A1

公开(公告)日：2017-12-21

申请号：US15188621

申请日：2016-06-21

Applicant: United Microelectronics Corp.

Inventor： Yi-Yu Wu ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask.

公开(公告)号：US09653549B2

公开(公告)日：2017-05-16

申请号：US15166271

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Jen Chen ,  Bin-Siang Tsai ,  Tsai-Yu Wen ,  Yu Shu Lin ,  Chin-Sheng Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L29/775 ,  H01L29/41

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02587 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

公开(公告)号：US09633955B1

公开(公告)日：2017-04-25

申请号：US15233926

申请日：2016-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jhih-Rong Huang ,  Bin-Siang Tsai

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329

Abstract: A semiconductor IC structure includes a semiconductor substrate, a multi-layered dielectric structure disposed on the semiconductor substrate, a first conductive layer disposed in the multi-layered dielectric structure, and a second conductive layer disposed on the multi-layered dielectric structure. The multi-layered dielectric structure further includes a first dielectric layer disposed on the semiconductor substrate, and a second dielectric layer disposed on the first dielectric layer. A coefficient of thermal expansion (CTE) of the first dielectric layer is larger than zero, and a CTE of the second dielectric layer is smaller than zero.

公开(公告)号：US09543195B1

公开(公告)日：2017-01-10

申请号：US15259041

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/32

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/76825 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 金属图案形成在第一电介质层上。 形成可修饰层以覆盖金属图案和第一介电层。 执行修改处理以修改金属图案的顶侧上的可修改层的一部分，从而形成顶部掩模。 执行去除过程以去除金属图案的侧壁上的可修饰层的一部分，但保留顶部掩模。 形成在顶部掩模之下和金属图案之间具有空隙的电介质层。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20250112184A1

公开(公告)日：2025-04-03

申请号：US18979653

申请日：2024-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

Abstract: A semiconductor device includes an aluminum (Al) pad on a substrate, a wire bonded onto the Al pad, a cobalt (Co) layer between and directly contacting the Al pad and the wire, and a Co—Pd alloy on the Al pad and divide the Co layer into a first portion, a second portion, and a third portion. Preferably, the wire includes a copper (Cu) wire and a palladium (Pd) layer coated on the Cu wire.