公开(公告)号：US09748222B2

公开(公告)日：2017-08-29

申请号：US15144836

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/7851

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

公开(公告)号：US20170194315A1

公开(公告)日：2017-07-06

申请号：US15464362

申请日：2017-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region. The gate set includes at least a first gate structure, a second gate structure, and a third gate structure.

公开(公告)号：US09691752B1

公开(公告)日：2017-06-27

申请号：US15096234

申请日：2016-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L27/0277 ,  H01L29/0619 ,  H01L29/7816

Abstract: An ESD protection device and a method of forming the same, the ESD device includes a substrate, a first doped well, a second doped well, a source and drain regions and a guard ring. The first doped well with a first conductive type is disposed in the substrate. The source and drain regions with the second conductive type are disposed in the first doped well. The guard ring with the first conductive type is also disposed in the first doped well and has a first portion extending along a first direction and a second portion extending along a second direction different from the first direction. The second doped well with the second conductive type is also disposed in the first doped well between the drain region and the second portion of the guard ring to in contact with the drain region in the first direction.

公开(公告)号：US20170125399A1

公开(公告)日：2017-05-04

申请号：US14924975

申请日：2015-10-28

Applicant: United Microelectronics Corp.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/861

Abstract: An electrostatic discharge (ESD) unit is described, including a first device, and a second device coupled to the first device in parallel. In an ESD event, the first device is turned on before the second device is turned on. The second device may be turned on by the turned-on first device to form an ESD path in the ESD event.

公开(公告)号：US09640524B2

公开(公告)日：2017-05-02

申请号：US14924708

申请日：2015-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yu Huang ,  Kuan-Cheng Su ,  Tien-Hao Tang ,  Ping-Jui Chen ,  Po-Ya Lai

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0277 ,  H01L27/0259 ,  H01L27/0886 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region.

公开(公告)号：US09331064B2

公开(公告)日：2016-05-03

申请号：US14742723

申请日：2015-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Tzu Wang ,  Ping-Chen Chang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L21/70 ,  H01L27/02 ,  H01L29/861 ,  H01L21/76 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/785 ,  H01L29/861

Abstract: A fin diode structure includes a doped well formed in a substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well isolated from ins of first conductivity type by STIs, at least one doped region of first conductivity type in the substrate between the fins of first conductivity type, the STIs and the doped well and connecting with the fins of first conductivity type, and at least one doped region of second conductivity type in the substrate between the fins of second conductivity type, the STIs and the doped well and connecting with the fins of second conductivity type. The doping concentration of the fins of first conductivity type is greater than that of the doped region of first conductivity type whose doping concentration is greater than that of the doped well of first conductivity type.

Abstract translation: 翅片二极管结构包括在衬底中形成的掺杂阱，第一导电类型的多个鳍和第二导电类型的多个翅片，其通过STI从与第一导电类型的绝缘体隔离的掺杂阱突出，至少一个掺杂区域 第一导电类型的翅片之间的衬底中的第一导电类型，STI和掺杂阱并且与第一导电类型的鳍连接并且在第二导电类型的鳍之间的衬底中的至少一个第二导电类型的掺杂区域 类型，STI和掺杂阱，并与第二导电类型的鳍连接。 第一导电类型的散热片的掺杂浓度大于其掺杂浓度大于第一导电类型的掺杂阱的第一导电类型的掺杂区域的掺杂浓度。

公开(公告)号：US20160118374A1

公开(公告)日：2016-04-28

申请号：US14986741

申请日：2016-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Ya-Ting Lin ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/87 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/402 ,  H01L29/7432 ,  H01L29/87

Abstract: An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Abstract translation: 静电放电保护结构包括隔离层，高电压P阱，N阱，P阱，N型导电的第一掺杂区，P型导电的第二掺杂区，第三掺杂区 N型导电性区域，P型导电性的第四掺杂区域，阳极和阴极。 隔离层设置在基板上。 高压P阱设置在隔离层上。 N阱设置在高压P阱中。 P阱设置在高电压P阱中，P阱与N阱分离。 第一和第二掺杂区域设置在N阱中。 第三和第四掺杂区域设置在P阱中。 阳极电连接到第一掺杂区域和第二掺杂区域，阴极电连接到第四掺杂区域。

公开(公告)号：US20150137255A1

公开(公告)日：2015-05-21

申请号：US14082529

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L27/0277 ,  H01L27/088

Abstract: A semiconductor device is described, including a substrate including a first area and a second area, a first MOS element of a first conductivity type in the first area, and a second MOS element of the first conductivity type in the second area. The first area is closer to a pick-up region of the substrate than the second area. The substrate has a second conductivity type. The bottom depth of a first electrical conduction path in the substrate in the first area is smaller than that of a second electrical conduction path in the substrate in the second area.

Abstract translation: 描述了一种半导体器件，包括包括第一区域和第二区域的衬底，第一区域中的第一导电类型的第一MOS元件和第二区域中的第一导电类型的第二MOS元件。 第一区域比第二区域更靠近基板的拾取区域。 衬底具有第二导电类型。 第一区域中的衬底中的第一导电通路的底部深度小于第二区域中的衬底中的第二导电通路的深度。

公开(公告)号：US20140284720A1

公开(公告)日：2014-09-25

申请号：US13848069

申请日：2013-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/78 ,  H01L23/60

CPC classification number: H01L27/0266 ,  H01L23/60 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，形成在衬底中的栅极的相应两侧处的漏极区域和源极区域，形成在漏极区域中的至少第一掺杂区域，以及至少第一 其中形成有第一掺杂区。 源区和漏区包括第一导电类型，第一掺杂区和第一阱包括第二导电类型，并且第一导电类型和第二导电类型彼此互补。