公开(公告)号：US09590739B2

公开(公告)日：2017-03-07

申请号：US14892578

申请日：2014-05-20

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Yaxin Zhang ,  Shen Qiao ,  Shixiong Liang ,  Ziqiang Yang ,  Zhihong Feng

IPC: H01L29/66 ,  H04B10/516 ,  H04B10/90 ,  H04B10/50

CPC classification number: H04B10/516 ,  H04B10/501 ,  H04B10/90

Abstract: Terahertz external modulator based on high electron mobility transistors belongs to the field of electromagnetic functional devices technology. This invention includes the semiconductor substrate (1), the epitaxial layer (2), and the modulation-unit array (4). The epitaxial layer (2) is set on the semiconductor substrate (1). The modulation-unit (4), the positive electrode (3), and the negative electrode (5) are all set on the epitaxial layer (2). The modulation-unit array includes at least three units with each of them is composed of high electron mobility transistors and metamaterial-structure. The gates of transistors connect to the negative electrode (5), and the sources and drains connect to the positive electrode (3). This invention is used for manipulation of spatial transmission terahertz waves. It could be operated at room temperatures, normal pressures, and non-vacuum condition. It does not need to load on the waveguide, thus is easy to package and use.

Abstract translation: 基于高电子迁移率晶体管的太赫兹外部调制器属于电磁功能器件技术领域。 本发明包括半导体衬底（1），外延层（2）和调制单元阵列（4）。 外延层（2）设置在半导体衬底（1）上。 调制单元（4），正极（3）和负极（5）全部设置在外延层（2）上。 调制单元阵列包括至少三个单元，每个单元由高电子迁移率晶体管和超材料结构组成。 晶体管的栅极连接到负极（5），源极和漏极连接到正极（3）。 本发明用于空间传输太赫兹波的操纵。 它可以在室温，正常压力和非真空条件下运行。 它不需要加载在波导上，因此易于封装和使用。

公开(公告)号：US20170003328A1

公开(公告)日：2017-01-05

申请号：US15146227

申请日：2016-05-04

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Qinchuan ZHANG ,  Kuojun YANG ,  Lianping GUO ,  Hao ZENG ,  Jia ZHAO ,  Jinpeng SONG

IPC: G01R19/25

CPC classification number: G01R13/0272 ,  G01R13/0254

Abstract: A method for measuring waveform capture rate (WRC) of DSO based on average dead time measurement. First generating ramp signal or symmetric triangular wave signal as base signal, a trigger signal, the frequency which is higher than the nominal maximum waveform capture rate of the DSO under measurement; secondly, setting the parameters of DSO for measuring; then obtaining a plurality of test signals by delaying base signal K times with different delay time, for each test signal, inputting it the trigger signal simultaneously to DSO, calculating dead time between two adjacent captured waveforms according to their initial voltages, finally calculating waveform capture rate based on average dead times. The waveform capture rate obtained can effectively reflect the overall capturing capacity of DSO, more tellingly, the waveform capturing capacity of acquisition system of DSO.

Abstract translation: 基于平均死区时间测量测量DSO的波形捕获率（WRC）的方法。 首先产生斜坡信号或对称三角波信号作为基准信号，触发信号，其频率高于测量的DSO的标称最大波形捕获率; 其次，设置测量用DSO的参数; 然后通过以不同的延迟时间延迟基本信号K次来获得多个测试信号，对于每个测试信号，将触发信号同时输入到DSO，根据它们的初始电压计算两个相邻捕获波形之间的死区时间，最后计算波形捕获 基于平均死亡时间。 获得的波形捕获率可以有效反映DSO的整体捕获能力，更具体地说，是DSO采集系统的波形捕获能力。

公开(公告)号：US09481926B2

公开(公告)日：2016-11-01

申请号：US14880148

申请日：2015-10-09

Applicant: University of Electronic Science and Technology of China

Inventor： Deen Gu ,  Tao Wang ,  Yadong Jiang

IPC: C23C14/08 ,  C23C14/35 ,  C23C14/00 ,  C23C14/34 ,  H01B1/02 ,  C23C14/58 ,  C01G31/02

CPC classification number: C23C14/083 ,  C01G31/02 ,  C23C14/0036 ,  C23C14/3464 ,  C23C14/35 ,  C23C14/352 ,  C23C14/58 ,  C23C14/5853 ,  H01B1/02

Abstract: A vanadium oxide thermo-sensitive film material with a high temperature coefficient of resistance (TCR) contains a rare earth element of Yttrium serving as a dopant in a preparation process. The vanadium oxide thermo-sensitive film material includes a substrate and a yttrium-doped vanadium oxide film layer. The yttrium-doped vanadium oxide film layer includes three elements of vanadium, oxygen and yttrium, wherein the atomic concentration of yttrium is at a range of 1%-8%, the atomic concentration of vanadium is at a range of 20-40% and the residue is oxygen. The method for preparing the vanadium oxide thermo-sensitive film material with high TCR includes a reactive magnetron sputtering method using a low-concentration yttrium-vanadium alloy target as a sputtering source or a reactive magnetron co-sputtering method using dual targets including a high-concentration yttrium-vanadium alloy target and a pure vanadium target as a co-sputtering source.

Abstract translation: 具有高耐温性（TCR）的氧化钒热敏膜材料在制备过程中含有作为掺杂剂的钇的稀土元素。 氧化钒热敏膜材料包括基底和掺杂钇的钒氧化物膜层。 钇掺杂钒氧化物膜层包括钒，氧和钇的三种元素，其中钇的原子浓度在1％-8％的范围内，钒的原子浓度在20-40％的范围内， 残留物是氧气。 制备具有高TCR的钒氧化物热敏膜材料的方法包括使用低浓度钇钒合金靶作为溅射源的反应性磁控管溅射法或使用包括高分子量的双靶的反应性磁控管共溅射法， 浓度钇钒合金靶和纯钒靶作为共溅射源。

公开(公告)号：US20160032443A1

公开(公告)日：2016-02-04

申请号：US14880148

申请日：2015-10-09

Applicant: University of Electronic Science and Technology of China

Inventor： Deen Gu ,  Tao Wang ,  Yadong Jiang

IPC: C23C14/08 ,  H01B1/02 ,  C23C14/34 ,  C23C14/35 ,  C23C14/00

CPC classification number: C23C14/083 ,  C01G31/02 ,  C23C14/0036 ,  C23C14/3464 ,  C23C14/35 ,  C23C14/352 ,  C23C14/58 ,  C23C14/5853 ,  H01B1/02

Abstract: A vanadium oxide thermo-sensitive film material with a high temperature coefficient of resistance (TCR) contains a rare earth element of Yttrium serving as a dopant in a preparation process. The vanadium oxide thermo-sensitive film material includes a substrate and a yttrium-doped vanadium oxide film layer. The yttrium-doped vanadium oxide film layer includes three elements of vanadium, oxygen and yttrium, wherein the atomic concentration of yttrium is at a range of 1%-8%, the atomic concentration of vanadium is at a range of 20-40% and the residue is oxygen. The method for preparing the vanadium oxide thermo-sensitive film material with high TCR includes a reactive magnetron sputtering method using a low-concentration yttrium-vanadium alloy target as a sputtering source or a reactive magnetron co-sputtering method using dual targets including a high-concentration yttrium-vanadium alloy target and a pure vanadium target as a co-sputtering source.

公开(公告)号：US09207208B2

公开(公告)日：2015-12-08

申请号：US14473793

申请日：2014-08-29

Applicant: University of Electronic Science and Technology of China

Inventor： Qishui Zhong ,  Hui Li ,  Dajin Chen ,  Baihua Li

IPC: H03K17/10 ,  G01N27/62 ,  H03K17/691

CPC classification number: G01N27/624 ,  H03K7/08 ,  H03K17/102 ,  H03K17/691

Abstract: An asymmetric waveform pulse generator comprises a metallic oxide semiconductor field effect transistor (MOSFET) bridge circuit, which includes a plurality of MOSFETs for inverting high voltage DC voltage to asymmetric waveform pulses. The asymmetric waveform pulse generator further comprises a pulse-width modulating (PWM) circuit for generating PWM signals, and a plurality of isolation driving circuits corresponding to the plurality of MOSFETs, for controlling switching on/off of the plurality of MOSFETs in the MOSFET bridge circuit based on the PWM signals generated by the PWM circuit. Each of the isolation driving circuits comprises an isolation transformer for isolating the MOSFET bridge circuit from the PWM circuit. A FAIMS ion detector employing the asymmetric waveform pulse generator is also disclosed.

Abstract translation: 非对称波形脉冲发生器包括金属氧化物半导体场效应晶体管（MOSFET）桥接电路，其包括用于将高压DC电压转换为非对称波形脉冲的多个MOSFET。 非对称波形脉冲发生器还包括用于产生PWM信号的脉冲宽度调制（PWM）电路和对应于多个MOSFET的多个隔离驱动电路，用于控制MOSFET桥中的多个MOSFET的导通/截止 基于由PWM电路产生的PWM信号的电路。 每个隔离驱动电路包括用于将MOSFET桥接电路与PWM电路隔离的隔离变压器。 还公开了采用非对称波形脉冲发生器的FAIMS离子检测器。

公开(公告)号：US08972812B2

公开(公告)日：2015-03-03

申请号：US13929758

申请日：2013-06-27

Applicant: University of Electronic Science and Technology of China

Inventor： Yajuan He ,  Tingting Xia ,  Tao Luo ,  Wubing Gan ,  Bo Zhang

IPC: G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  G01R31/317

CPC classification number: G01R31/317 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/152 ,  Y02D10/172

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract translation: 一种流水线处理器，包括几级的组合逻辑，电压调节器，计数器，比较器和多个级寄存器。 每个级寄存器被布置在组合逻辑的两个相邻级之间。 级寄存器包括触发器，锁存器，异或门和MUX模块。 当寄存器时钟的高电平到来时，触发器在上升沿锁存第一数据，并且锁存器在高电平期间接收第二数据。 由触发器和锁存器锁存的数据分别由XOR门进行比较。 如果它们相同，则XOR门的输出误差为低电平，触发器的输出被传送到下一级。 否则，异或门的输出误差为高电平，并将锁存器的输出传送到下一级。

公开(公告)号：US08907650B2

公开(公告)日：2014-12-09

申请号：US13637237

申请日：2011-02-28

Applicant: Shaowei Zhen ,  Ping Luo ,  Ruhui Yang ,  Kang Yang ,  Bo Zhang

Inventor： Shaowei Zhen ,  Ping Luo ,  Ruhui Yang ,  Kang Yang ,  Bo Zhang

IPC: G05F3/16 ,  G05F3/30

CPC classification number: G05F3/16 ,  G05F3/30 ,  Y10S323/907

Abstract: This invention involves a bandgap reference circuit in IC. The temperature coefficient of conventional bandgap reference is large and the higher order compensation is difficult to implement. This invention provides an adaptive compensated bandgap reference which solves the problem only using lower order (first order) temperature coefficient compensation. The invention adopts segmental compensation circuit to realize adaptive segmental compensation of bandgap reference with low temperature coefficient. The technical solution includes traditional bandgap voltage reference circuit and adaptive feedback compensation circuit which consists of sample and hold circuit, voltage comparator and control module. This invention controls the bandgap voltage reference through systematical view and it has high process compatibility. This invention can find the best temperature characteristic curve adaptively, the output voltage has low temperature coefficient, meeting the requirement of fabrication process, the implementation is simple with small area. This invention relates to integrated circuits.

Abstract translation: 本发明涉及IC中的带隙基准电路。 常规带隙基准的温度系数大，难以实现较高阶补偿。 本发明提供了一种仅使用低阶（一阶）温度系数补偿来解决问题的自适应补偿带隙基准。 本发明采用分段补偿电路，实现低温系数带隙参考自适应分段补偿。 技术方案包括传统的带隙电压参考电路和自适应反馈补偿电路，由采样保持电路，电压比较器和控制模块组成。 本发明通过系统的视图控制带隙电压参考，并具有较高的工艺兼容性。 本发明可以自适应地找到最佳的温度特性曲线，输出电压温度系数低，满足制造工艺要求，实现面积小。 本发明涉及集成电路。

公开(公告)号：US08890280B2

公开(公告)日：2014-11-18

申请号：US13033701

申请日：2011-02-24

Applicant: Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

Inventor： Xiaorong Luo ,  Guoliang Yao ,  Tianfei Lei ,  Yuangang Wang ,  Bo Zhang

IPC: H01L23/58 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7397

Abstract: The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high.

Abstract translation: 本发明涉及一种半导体器件。 该器件包括半导体衬底。 半导体漂移区位于半导体衬底上。 半导体漂移区域包括第一导电类型的半导体区域和第二导电类型的半导体区域。 第一导电类型的半导体区域和第二导电类型的半导体区域形成超结构结构。 高K电介质在半导体衬底上。 高K电介质与第二导电类型的半导体区域相邻。 有源区位于半导体漂移区上。 沟槽栅极结构位于高K电介质上，沟槽栅极结构邻近有源区。 第二导电类型的半导体区域通过浅角离子注入形成，其宽度窄并且其浓度高。

公开(公告)号：US08837551B2

公开(公告)日：2014-09-16

申请号：US13589930

申请日：2012-08-20

Applicant: Zhaoyun Duan ,  Xin Guo ,  Chen Guo ,  Yubin Gong ,  Min Chen

Inventor： Zhaoyun Duan ,  Xin Guo ,  Chen Guo ,  Yubin Gong ,  Min Chen

IPC: H01S3/09

CPC classification number: H01J25/00

Abstract: A method for generating high power electromagnetic radiation based on double-negative metamaterial (DNM), includes providing electrons of an electron beam moving in a vacuum close to an interface between the DNM and the vacuum at a predetermined average speed larger than a phase velocity of an electromagnetic wave propagating in the DNM so as to generate coherent high power radiation. The method can be applied but not limited to high power and compact Terahertz radiation sources and Cherenkov particle detectors and emitters.

公开(公告)号：US08716794B2

公开(公告)日：2014-05-06

申请号：US13131779

申请日：2010-08-10

Applicant: Xiaorong Luo ,  Florin Udrea

Inventor： Xiaorong Luo ,  Florin Udrea

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7809 ,  H01L29/7812

Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration. The device in the present invention is particularly suitable for power integrated circuits and RF power integrated circuits.

Abstract translation: 本发明涉及半导体功率器件和功率集成电路（IC）。 本发明的横向SOI MOSFET包括延伸到电介质掩埋层的沟槽栅极，漂移区域中的一个或多个电介质沟槽以及所述电介质沟槽中的掩埋栅极。 电介质在所述电介质沟槽中的介电常数低于所述有源层的介电常数。 首先，所述电介质沟槽不仅大大提高了击穿电压，还降低了间距尺寸。 其次，沟槽栅极使垂直方向上的有效导电区域变宽。 第三，所述沟槽栅极和掩埋栅极的双栅极增加了沟道和电流密度。 从而，降低了特定导通电阻和功率损耗。 本发明的器件具有高电压，高速，低功耗，低成本，易集成等诸多优点。 本发明的器件特别适用于功率集成电路和RF功率集成电路。