公开(公告)号：US20090159872A1

公开(公告)日：2009-06-25

申请号：US12359479

申请日：2009-01-26

Applicant: Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin K. Brask ,  Robert S. Chau

Inventor： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Marko Radosavljevic ,  Amlan Majumdar ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L29/08

CPC classification number: H01L51/102 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545 ,  H01L51/105

Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

Abstract translation: 通过形成金属的栅电极，可以在碳纳米管晶体管中减少双极传导。 可以形成具有与栅电极不同的功函数的金属侧壁间隔物以支撑金属栅电极。

公开(公告)号：US20090001350A1

公开(公告)日：2009-01-01

申请号：US11823516

申请日：2007-06-28

Applicant: Mantu K. Hudait ,  Suman Datta ,  Robert S. Chau ,  Marko Radosavljevic

Inventor： Mantu K. Hudait ,  Suman Datta ,  Robert S. Chau ,  Marko Radosavljevic

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L29/7783 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02584 ,  H01L29/66462 ,  H01L29/7784

Abstract: One embodiment of the invention includes a high hole mobility p-channel GaAsySb1-y quantum well with a silicon substrate and an InxAl1-xAs barrier layer.

Abstract translation: 本发明的一个实施方案包括具有硅衬底和In x Al 1-xAs阻挡层的高空穴迁移率p沟道GaAsySb1-y量子阱。

公开(公告)号：US20080151603A1

公开(公告)日：2008-06-26

申请号：US12072971

申请日：2008-02-28

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC: G11C11/34

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

Abstract translation: 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20080142786A1

公开(公告)日：2008-06-19

申请号：US11610415

申请日：2006-12-13

Applicant: Suman Datta ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Marko Radosavljevic

Inventor： Suman Datta ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Marko Radosavljevic

IPC: H01L29/12

CPC classification number: H01L29/7783 ,  H01L29/517

Abstract: A group III-V material device may have a capping layer on a barrier region, which may provide a high quality interface for a high-k gate dielectric. This may improve the performance of the device by reducing gate leakage and preserve the high-mobility properties of the quantum well channel region of the device.

Abstract translation: III-V族材料器件可以在阻挡区域上具有覆盖层，这可为高k栅极电介质提供高质量的界面。 这可以通过减少栅极泄漏并且保持器件的量子阱沟道区域的高迁移率特性来改善器件的性能。

公开(公告)号：US20080108214A1

公开(公告)日：2008-05-08

申请号：US11299228

申请日：2005-12-09

Applicant: Amlan Majumdar ,  Robert S. Chau ,  Justin K. Brask ,  Marko Radosavljevic ,  Matthew V. Metz

Inventor： Amlan Majumdar ,  Robert S. Chau ,  Justin K. Brask ,  Marko Radosavljevic ,  Matthew V. Metz

IPC: H01L21/44

CPC classification number: H01L51/0545 ,  B82Y10/00 ,  H01L51/0048

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming at least one metal source/drain on a gate dielectric, wherein the at least one metal source/drain is adjacent to a channel region, wherein the channel region comprises at least one carbon nanotube.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括在栅极电介质上形成至少一个金属源极/漏极，其中至少一个金属源极/漏极与沟道区相邻，其中沟道区包括至少一个碳纳米管。

公开(公告)号：US20070141790A1

公开(公告)日：2007-06-21

申请号：US11638333

申请日：2006-12-12

Applicant: Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

Inventor： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

IPC: H01L21/336

CPC classification number: H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

Abstract translation: 描述了在碳纳米管内形成能量阱的结构。 该结构包括掺杂半导体区域和未掺杂的半导体区域。 碳纳米管位于掺杂半导体区域和未掺杂的半导体区域之间。 该结构还包括δ掺杂半导体区域。 未掺杂的半导体区域在碳纳米管和δ掺杂区之间。 该掺杂掺杂的δ掺杂半导体区域与掺杂半导体区域的掺杂相反。

公开(公告)号：US20070001219A1

公开(公告)日：2007-01-04

申请号：US11173866

申请日：2005-06-30

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Uday Shah ,  Suman Datta ,  Robert Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Brian Doyle ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Uday Shah ,  Suman Datta ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Abstract translation: 一种用于纳米尺度通道器件的接触结构，其具有耦合到具有多个平行半导体器件的器件的源极或漏极区域之间并具有接触结构的接触结构。 接触结构能够接触具有亚光刻间距的平行半导体本体。

公开(公告)号：US20060220074A1

公开(公告)日：2006-10-05

申请号：US11096984

申请日：2005-03-31

Applicant: Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

Inventor： Suman Datta ,  Marko Radosavljevic ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Amlan Majumdar ,  Robert Chau

IPC: H01L29/94

CPC classification number: H01L51/0508 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0052 ,  Y10S977/762

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

Abstract translation: 描述了在碳纳米管内形成能量阱的结构。 该结构包括掺杂半导体区域和未掺杂的半导体区域。 碳纳米管位于掺杂半导体区域和未掺杂的半导体区域之间。 该结构还包括δ掺杂半导体区域。 未掺杂的半导体区域在碳纳米管和δ掺杂区之间。 该掺杂掺杂的δ掺杂半导体区域与掺杂半导体区域的掺杂相反。

公开(公告)号：US20060202266A1

公开(公告)日：2006-09-14

申请号：US11080765

申请日：2005-03-14

Applicant: Marko Radosavljevic ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Amian Majumdar ,  Robert Chau

Inventor： Marko Radosavljevic ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Amian Majumdar ,  Robert Chau

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/41791 ,  H01L21/3141 ,  H01L23/485 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/78621 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Abstract translation: 一种半导体器件，包括形成在形成在半导体膜上的栅极电介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上的沟道区域附近。 源极和漏极区域各自包括与半导体沟道相邻并与其接触的半导体部分和与半导体部分相邻并与其接触的金属部分。

公开(公告)号：US20060068591A1

公开(公告)日：2006-03-30

申请号：US11240440

申请日：2005-09-29

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Brian Doyle ,  Justin Brask ,  Robert Chau

IPC: H01L21/302

CPC classification number: H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Abstract translation: 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许在沟道区下方除去氧化物。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。