公开(公告)号：US20240234350A9

公开(公告)日：2024-07-11

申请号：US17989633

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L25/16 ,  H01L27/1203 ,  H01L28/90 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

公开(公告)号：US20240222437A1

公开(公告)日：2024-07-04

申请号：US18608890

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/66431 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.

公开(公告)号：US20240222369A1

公开(公告)日：2024-07-04

申请号：US18098710

申请日：2023-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Peng-Hsiu Chen ,  Su-Ming Hsieh ,  Ying-Ren Chen

IPC: H01L27/08 ,  H01L29/66 ,  H01L29/93

CPC classification number: H01L27/0808 ,  H01L29/66174 ,  H01L29/93

Abstract: The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.

公开(公告)号：US12029138B2

公开(公告)日：2024-07-02

申请号：US18201741

申请日：2023-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  H01L27/0248 ,  H10B61/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US12029044B2

公开(公告)日：2024-07-02

申请号：US18127651

申请日：2023-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

公开(公告)号：US12027604B2

公开(公告)日：2024-07-02

申请号：US18215787

申请日：2023-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US12027600B2

公开(公告)日：2024-07-02

申请号：US18201769

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20240215251A1

公开(公告)日：2024-06-27

申请号：US18602040

申请日：2024-03-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10B43/35 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/35 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate disposed on a substrate, a dielectric layer and two charge trapping layers, wherein the dielectric layer is disposed between the substrate and the memory gate, and the two charge trapping layers are disposed at two opposite sides of the memory gate, wherein each of the charge trapping layers comprises an L-shape cross-sectional profile, and two selective gates disposed on the substrate, thereby constituting a two bit memory cell, wherein a top surface of each selective gate is higher than a top surface of the memory gate.

公开(公告)号：US20240210816A1

公开(公告)日：2024-06-27

申请号：US18165937

申请日：2023-02-08

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

IPC: G03F1/70 ,  G03F1/36 ,  G06F30/392

CPC classification number: G03F1/70 ,  G03F1/36 ,  G06F30/392

Abstract: A method includes providing a layout pattern to a computer system. The layout pattern includes a first pattern, a second pattern, and a third pattern. A central line defined by connecting a line end of the second pattern and a line end of the third pattern overlaps with a middle portion of the first pattern. An optical proximity correction (OPC) is performed on the layout pattern to form a first auxiliary pattern. The first auxiliary pattern includes a first stripe pattern and a second stripe pattern both extending from the line end of the second pattern. The second stripe pattern is closer to the first pattern than the first stripe pattern, and an extending length of the second stripe pattern is less than an extending length of the first stripe pattern. The layout pattern and the first auxiliary pattern are outputted through the computer system onto a photomask.

公开(公告)号：US12022739B2

公开(公告)日：2024-06-25

申请号：US18116277

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.