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146 条记录 (耗时 0.027 秒)

    Semiconductor Constructions, Memory Cells, Memory Arrays and Methods of Forming Memory Cells
    123.
    发明申请
    Semiconductor Constructions, Memory Cells, Memory Arrays and Methods of Forming Memory Cells 有权
    半导体构造，存储单元，存储器阵列和形成记忆单元的方法

    公开(公告)号：US20140021431A1

    公开(公告)日：2014-01-23

    申请号：US13551975

    申请日：2012-07-18

    申请人： Fabio Pellizzer ,  Cinzia Perrone

    发明人： Fabio Pellizzer ,  Cinzia Perrone

    IPC分类号： H01L47/00 ,  H01L21/02

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2445 ,  H01L29/02 ,  H01L45/06 ,  H01L45/12 ,  H01L45/124 ,  H01L45/141 ,  H01L45/144 ,  H01L45/145 ,  H01L45/1666 ,  H01L45/1691

    摘要： Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells.

    摘要翻译： 一些实施例包括直接在间隔开的节点上的具有氧敏感结构的结构。 每个氧敏感结构包括具有沿节点顶表面的水平部分和从水平部分向上延伸的非水平部分的倾斜板。 每个倾斜板具有内侧壁，其中在非水平部分和水平部分之间形成内角，与侧壁相对的外侧壁和侧边缘。 位线在氧敏感结构之上，并且具有从氧敏感结构的侧边缘向上延伸的侧壁。 非含氧结构沿着内侧壁，沿着外侧壁沿着横向边缘，位线以及沿着位线的侧壁沿着内侧。 一些实施例包括存储器阵列和形成存储器单元的方法。

    Method Arrays and Methods of Forming Memory Cells
    127.
    发明申请
    Method Arrays and Methods of Forming Memory Cells 有权
    形成记忆细胞的方法数组和方法

    公开(公告)号：US20130126822A1

    公开(公告)日：2013-05-23

    申请号：US13298962

    申请日：2011-11-17

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    IPC分类号： H01L45/00 ,  H01L21/62

    CPC分类号： H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

    摘要： Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

    摘要翻译： 一些实施例包括形成存储器单元的方法。 堆叠包括在导电区域上的超声波材料。 堆叠被图案化成沿着第一方向延伸的轨道。 轨道被图案化为支柱。 导电线形成在超声波材料上。 导电线沿着与第一方向相交的第二方向延伸。 导电线沿着第二方向互连柱。 一些实施例包括具有沿着第一方向延伸的第一导电线的存储器阵列。 这些线包含半导体材料的n型掺杂区域。 支柱超过第一导线，并且包含n型掺杂区域的台面以及p型掺杂区域和超声材料。 第二导电线在超声波材料之上并且沿与第一方向相交的第二方向延伸。 第二导电线沿着第二方向互连柱。

    Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers
    128.
    发明授权
    Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers 有权
    用于制造包括垂直双极结型晶体管和具有间隔物的CMOS晶体管的存储器件的工艺

    公开(公告)号：US08293598B2

    公开(公告)日：2012-10-23

    申请号：US12557396

    申请日：2009-09-10

    申请人： Fabio Pellizzer ,  Cristina Casellato ,  Michele Magistretti ,  Roberto Colombo ,  Lucilla Brattico

    发明人： Fabio Pellizzer ,  Cristina Casellato ,  Michele Magistretti ,  Roberto Colombo ,  Lucilla Brattico

    IPC分类号： H01L21/8238 ,  H01L27/06

    CPC分类号： H01L27/0623 ,  G11C13/0004 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/2445 ,  H01L29/6656 ,  H01L29/6659 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    摘要： A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.

    摘要翻译： 在半导体本体中形成用于存储器件的双极选择晶体管和电路MOS晶体管。 双极选择晶体管通过注入掩埋集电器，在掩埋集电极上注入基极区域，在半导体主体上形成硅化物保护掩模，以及注入发射极区域和控制接触区域而形成。 电路MOS晶体管通过在半导体主体上限定栅极形成，在栅极的侧面上形成横向间隔物，并在侧面间隔物的侧面上注入源极和漏极区域。 然后，以自对准的方式在发射极，基极接触，源极和漏极区域以及栅极上形成硅化物区域。 横向间隔物是包括至少两个不同层的多层结构，其中之一用于在双极选择晶体管上形成硅化物保护掩模。 因此，横向间隔件的尺寸与硅化物防护罩的厚度分离。